make build system more generic
This commit is contained in:
Sebastien Bourdeauducq
parent
4a3a1d02e9
commit
fdff1ae5f8
108
make.py
108
make.py
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@ -1,77 +1,69 @@
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#!/usr/bin/env python3
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import argparse, os, importlib, subprocess
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import argparse, importlib, subprocess
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from mibuild.tools import write_to_file
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from misoclib.gensoc import cpuif
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from misoclib.s6ddrphy import initsequence
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import top, jtag
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import jtag
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def build(platform_name, build_bitstream, build_header, csr_csv_filename, *soc_args, **soc_kwargs):
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platform_module = importlib.import_module("mibuild.platforms."+platform_name)
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platform = platform_module.Platform()
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soc = top.SoC(platform, *soc_args, **soc_kwargs)
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def _get_args():
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parser = argparse.ArgumentParser(description="MiSoC - a high performance SoC based on Migen.")
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parser.add_argument("-p", "--platform", default="mixxeo", help="platform to build for")
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parser.add_argument("-t", "--target", default="mlabs_video", help="SoC type to build")
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parser.add_argument("-s", "--sub-target", default="", help="variant of the SoC type to build")
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platform.add_platform_command("""
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INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
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INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
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parser.add_argument("-B", "--no-bitstream", default=False, action="store_true", help="do not build bitstream file")
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parser.add_argument("-H", "--no-header", default=False, action="store_true", help="do not build C header files with CSR/IRQ/SDRAM_PHY definitions")
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parser.add_argument("-c", "--csr-csv", default="", help="save CSR map into CSV file")
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PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
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PIN "dviout_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
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""")
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parser.add_argument("-l", "--load", default=False, action="store_true", help="load bitstream to FPGA volatile memory")
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parser.add_argument("-f", "--flash", default=False, action="store_true", help="load bitstream to flash")
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if hasattr(soc, "fb"):
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platform.add_platform_command("""
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NET "{vga_clk}" TNM_NET = "GRPvga_clk";
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NET "sys_clk" TNM_NET = "GRPsys_clk";
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TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
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""", vga_clk=soc.fb.driver.clocking.cd_pix.clk)
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for d in ["mxcrg", "minimac3"]:
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platform.add_source_dir(os.path.join("verilog", d))
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platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
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"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
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"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
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"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
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"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
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"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
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"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
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platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
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if build_bitstream:
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build_name = "soc-"+platform_name
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platform.build(soc, build_name=build_name)
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subprocess.call(["tools/byteswap", "build/"+build_name+".bin", "build/"+build_name+".fpg"])
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else:
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soc.finalize()
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if build_header:
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csr_header = cpuif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
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write_to_file("software/include/hw/csr.h", csr_header)
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sdram_phy_header = initsequence.get_sdram_phy_header(soc.ddrphy)
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write_to_file("software/include/hw/sdram_phy.h", sdram_phy_header)
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if csr_csv_filename:
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csr_csv = cpuif.get_csr_csv(soc.csr_base, soc.csrbankarray)
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write_to_file(csr_csv_filename, csr_csv)
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return parser.parse_args()
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def main():
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parser = argparse.ArgumentParser(description="MiSoC - a high performance SoC based on Migen.")
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parser.add_argument("-p", "--platform", default="mixxeo", help="platform to build for")
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parser.add_argument("-B", "--no-bitstream", default=False, action="store_true", help="do not build bitstream file")
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parser.add_argument("-H", "--no-header", default=False, action="store_true", help="do not build C header files with CSR/IRQ/SDRAM_PHY defs")
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parser.add_argument("-c", "--csr-csv", default="", help="save CSR map in CSV file")
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parser.add_argument("-l", "--load", default=False, action="store_true", help="load bitstream to SRAM")
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parser.add_argument("-f", "--flash", default=False, action="store_true", help="load bitstream to flash")
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parser.add_argument("-m", "--with-memtest", default=False, action="store_true", help="include memtest cores")
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args = parser.parse_args()
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args = _get_args()
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platform_module = importlib.import_module("mibuild.platforms." + args.platform)
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target_module = importlib.import_module("targets." + args.target)
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platform = platform_module.Platform()
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if args.sub_target:
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top_class = getattr(target_module, args.sub_target)
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else:
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top_class = target_module.get_default_subtarget(platform)
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build_name = top_class.__name__.lower() + "-" + args.platform
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soc = top_class(platform)
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if not args.no_bitstream:
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platform.build(soc, build_name=build_name)
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subprocess.call(["tools/byteswap",
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"build/" + build_name + ".bin",
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"build/" + build_name + ".fpg"])
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else:
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soc.finalize()
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if not args.no_header:
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boilerplate = """/*
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* Platform: {}
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* Target: {}
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* Subtarget: {}
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*/
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""".format(args.platform, args.target, top_class.__name__)
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csr_header = cpuif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
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write_to_file("software/include/hw/csr.h", boilerplate + csr_header)
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sdram_phy_header = initsequence.get_sdram_phy_header(soc.ddrphy)
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write_to_file("software/include/hw/sdram_phy.h", boilerplate + sdram_phy_header)
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if args.csr_csv:
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csr_csv = cpuif.get_csr_csv(soc.csr_base, soc.csrbankarray)
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write_to_file(args.csr_csv, csr_csv)
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build(args.platform, not args.no_bitstream, not args.no_header, args.csr_csv, args.with_memtest)
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if args.load:
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jtag.load("build/soc-"+args.platform+".bit")
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jtag.load("build/" + build_name + ".bit")
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if args.flash:
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jtag.flash("build/soc-"+args.platform+".fpg")
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jtag.flash("build/" + build_name + ".fpg")
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if __name__ == "__main__":
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main()
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@ -1,3 +1,4 @@
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import os
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from operator import itemgetter
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from collections import defaultdict
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from math import ceil
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@ -51,7 +52,17 @@ class GenSoC(Module):
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self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
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self.submodules.identifier = identifier.Identifier(self.known_platform_id[platform.name], int(clk_freq),
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log2_int(l2_size) if l2_size else 0)
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self.submodules.timer0 = timer.Timer()
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self.submodules.timer0 = timer.Timer()
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# add LM32 verilog sources
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platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
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"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
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"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
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"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
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"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
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"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
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"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
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platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
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def add_wb_master(self, wbm):
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if self.finalized:
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@ -1,3 +1,4 @@
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import os
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from fractions import Fraction
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from migen.fhdl.std import *
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@ -41,7 +42,7 @@ class MiniSoC(SDRAMSoC):
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}
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interrupt_map.update(SDRAMSoC.interrupt_map)
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def __init__(self, platform, with_memtest):
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def __init__(self, platform, with_memtest=False):
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SDRAMSoC.__init__(self, platform,
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clk_freq=(83 + Fraction(1, 3))*1000000,
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sram_size=4096,
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@ -88,6 +89,16 @@ class MiniSoC(SDRAMSoC):
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self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
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self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
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]
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platform.add_platform_command("""
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INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
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INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
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PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
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""")
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# add Verilog sources
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for d in ["mxcrg", "minimac3"]:
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platform.add_source_dir(os.path.join("verilog", d))
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def _get_vga_dvi(platform):
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try:
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@ -98,21 +109,39 @@ def _get_vga_dvi(platform):
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pads_dvi = platform.request("dvi_out")
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except ConstraintError:
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pads_dvi = None
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else:
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platform.add_platform_command("""
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PIN "dviout_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
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""")
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return pads_vga, pads_dvi
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def _add_vga_tig(platform, fb):
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platform.add_platform_command("""
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NET "{vga_clk}" TNM_NET = "GRPvga_clk";
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NET "sys_clk" TNM_NET = "GRPsys_clk";
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TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
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""", vga_clk=fb.driver.clocking.cd_pix.clk)
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class FramebufferSoC(MiniSoC):
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def __init__(self, platform, with_memtest):
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def __init__(self, platform, with_memtest=False):
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MiniSoC.__init__(self, platform, with_memtest)
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pads_vga, pads_dvi = _get_vga_dvi(platform)
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self.submodules.fb = framebuffer.Framebuffer(pads_vga, pads_dvi, self.lasmixbar.get_master())
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_add_vga_tig(platform, self.fb)
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class VideomixerSoC(MiniSoC):
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def __init__(self, platform, with_memtest):
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def __init__(self, platform, with_memtest=False):
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MiniSoC.__init__(self, platform, with_memtest)
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pads_vga, pads_dvi = _get_vga_dvi(platform)
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self.submodules.fb = framebuffer.MixFramebuffer(pads_vga, pads_dvi,
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self.lasmixbar.get_master(), self.lasmixbar.get_master())
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_add_vga_tig(platform, self.fb)
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self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), self.lasmixbar.get_master())
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self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), self.lasmixbar.get_master())
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SoC = VideomixerSoC
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def get_default_subtarget(platform):
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if platform.name == "mixxeo":
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return VideomixerSoC
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else:
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return FramebufferSoC
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