make build system more generic

make.py

@@ -1,77 +1,69 @@
 #!/usr/bin/env python3
 
-import argparse, os, importlib, subprocess
+import argparse, importlib, subprocess
 
 from mibuild.tools import write_to_file
 
 from misoclib.gensoc import cpuif
 from misoclib.s6ddrphy import initsequence
-import top, jtag
+import jtag
 
-def build(platform_name, build_bitstream, build_header, csr_csv_filename, *soc_args, **soc_kwargs):
+def _get_args():
-	platform_module = importlib.import_module("mibuild.platforms."+platform_name)
+	parser = argparse.ArgumentParser(description="MiSoC - a high performance SoC based on Migen.")
-	platform = platform_module.Platform()
+
-	soc = top.SoC(platform, *soc_args, **soc_kwargs)
+	parser.add_argument("-p", "--platform", default="mixxeo", help="platform to build for")
+	parser.add_argument("-t", "--target", default="mlabs_video", help="SoC type to build")
+	parser.add_argument("-s", "--sub-target", default="", help="variant of the SoC type to build")
 	
-	platform.add_platform_command("""
+	parser.add_argument("-B", "--no-bitstream", default=False, action="store_true", help="do not build bitstream file")
-INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
+	parser.add_argument("-H", "--no-header", default=False, action="store_true", help="do not build C header files with CSR/IRQ/SDRAM_PHY definitions")
-INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
+	parser.add_argument("-c", "--csr-csv", default="", help="save CSR map into CSV file")
 
-PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
+	parser.add_argument("-l", "--load", default=False, action="store_true", help="load bitstream to FPGA volatile memory")
-PIN "dviout_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
+	parser.add_argument("-f", "--flash", default=False, action="store_true", help="load bitstream to flash")
-""")
 
-	if hasattr(soc, "fb"):
+	return parser.parse_args()
-		platform.add_platform_command("""
-NET "{vga_clk}" TNM_NET = "GRPvga_clk";
-NET "sys_clk" TNM_NET = "GRPsys_clk";
-TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
-TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
-""", vga_clk=soc.fb.driver.clocking.cd_pix.clk)
-
-	for d in ["mxcrg", "minimac3"]:
-		platform.add_source_dir(os.path.join("verilog", d))
-	platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"), 
-		"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
-		"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
-		"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
-		"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
-		"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
-		"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
-	platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
-
-	if build_bitstream:
-		build_name = "soc-"+platform_name
-		platform.build(soc, build_name=build_name)
-		subprocess.call(["tools/byteswap", "build/"+build_name+".bin", "build/"+build_name+".fpg"])
-	else:
-		soc.finalize()
-	if build_header:
-		csr_header = cpuif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
-		write_to_file("software/include/hw/csr.h", csr_header)
-		
-		sdram_phy_header = initsequence.get_sdram_phy_header(soc.ddrphy)
-		write_to_file("software/include/hw/sdram_phy.h", sdram_phy_header)
-	if csr_csv_filename:
-		csr_csv = cpuif.get_csr_csv(soc.csr_base, soc.csrbankarray)
-		write_to_file(csr_csv_filename, csr_csv)
 
 def main():
-	parser = argparse.ArgumentParser(description="MiSoC - a high performance SoC based on Migen.")
+	args = _get_args()
-	parser.add_argument("-p", "--platform", default="mixxeo", help="platform to build for")
+
-	parser.add_argument("-B", "--no-bitstream", default=False, action="store_true", help="do not build bitstream file")
+	platform_module = importlib.import_module("mibuild.platforms." + args.platform)
-	parser.add_argument("-H", "--no-header", default=False, action="store_true", help="do not build C header files with CSR/IRQ/SDRAM_PHY defs")
+	target_module = importlib.import_module("targets." + args.target)
-	parser.add_argument("-c", "--csr-csv", default="", help="save CSR map in CSV file")
+	platform = platform_module.Platform()
-	parser.add_argument("-l", "--load", default=False, action="store_true", help="load bitstream to SRAM")
+	if args.sub_target:
-	parser.add_argument("-f", "--flash", default=False, action="store_true", help="load bitstream to flash")
+		top_class = getattr(target_module, args.sub_target)
-	parser.add_argument("-m", "--with-memtest", default=False, action="store_true", help="include memtest cores")
+	else:
-	args = parser.parse_args()
+		top_class = target_module.get_default_subtarget(platform)
+	build_name = top_class.__name__.lower() + "-" + args.platform
+	soc = top_class(platform)
+
+	if not args.no_bitstream:
+		platform.build(soc, build_name=build_name)
+		subprocess.call(["tools/byteswap",
+			"build/" + build_name + ".bin",
+			"build/" + build_name + ".fpg"])
+	else:
+		soc.finalize()
+	if not args.no_header:
+		boilerplate = """/*
+ * Platform: {}
+ * Target: {}
+ * Subtarget: {}
+ */
+
+""".format(args.platform, args.target, top_class.__name__)
+		csr_header = cpuif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
+		write_to_file("software/include/hw/csr.h", boilerplate + csr_header)
+		sdram_phy_header = initsequence.get_sdram_phy_header(soc.ddrphy)
+		write_to_file("software/include/hw/sdram_phy.h", boilerplate + sdram_phy_header)
+	if args.csr_csv:
+		csr_csv = cpuif.get_csr_csv(soc.csr_base, soc.csrbankarray)
+		write_to_file(args.csr_csv, csr_csv)
 
-	build(args.platform, not args.no_bitstream, not args.no_header, args.csr_csv, args.with_memtest)
 	if args.load:
-		jtag.load("build/soc-"+args.platform+".bit")
+		jtag.load("build/" + build_name + ".bit")
 	if args.flash:
-		jtag.flash("build/soc-"+args.platform+".fpg")
+		jtag.flash("build/" + build_name + ".fpg")
 
 if __name__ == "__main__":
 	main()

misoclib/gensoc/__init__.py

@@ -1,3 +1,4 @@
+import os
 from operator import itemgetter
 from collections import defaultdict
 from math import ceil
@@ -51,7 +52,17 @@ class GenSoC(Module):
 		self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
 		self.submodules.identifier = identifier.Identifier(self.known_platform_id[platform.name], int(clk_freq),
 			log2_int(l2_size) if l2_size else 0)
-		self.submodules.timer0 = timer.Timer()		
+		self.submodules.timer0 = timer.Timer()
+
+		# add LM32 verilog sources
+		platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"), 
+			"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
+			"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
+			"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
+			"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
+			"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
+			"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
+		platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
 
 	def add_wb_master(self, wbm):
 		if self.finalized:

targets/mlabs_video.py

@@ -1,3 +1,4 @@
+import os
 from fractions import Fraction
 
 from migen.fhdl.std import *
@@ -41,7 +42,7 @@ class MiniSoC(SDRAMSoC):
 	}
 	interrupt_map.update(SDRAMSoC.interrupt_map)
 
-	def __init__(self, platform, with_memtest):
+	def __init__(self, platform, with_memtest=False):
 		SDRAMSoC.__init__(self, platform,
 			clk_freq=(83 + Fraction(1, 3))*1000000,
 			sram_size=4096,
@@ -88,6 +89,16 @@ class MiniSoC(SDRAMSoC):
 			self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
 			self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
 		]
+		platform.add_platform_command("""
+INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
+INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
+
+PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
+""")
+
+		# add Verilog sources
+		for d in ["mxcrg", "minimac3"]:
+			platform.add_source_dir(os.path.join("verilog", d))
 		
 def _get_vga_dvi(platform):
 	try:
@@ -98,21 +109,39 @@ def _get_vga_dvi(platform):
 		pads_dvi = platform.request("dvi_out")
 	except ConstraintError:
 		pads_dvi = None
+	else:
+		platform.add_platform_command("""
+PIN "dviout_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
+""")
 	return pads_vga, pads_dvi
 
+def _add_vga_tig(platform, fb):
+	platform.add_platform_command("""
+NET "{vga_clk}" TNM_NET = "GRPvga_clk";
+NET "sys_clk" TNM_NET = "GRPsys_clk";
+TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
+TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
+""", vga_clk=fb.driver.clocking.cd_pix.clk)
+
 class FramebufferSoC(MiniSoC):
-	def __init__(self, platform, with_memtest):
+	def __init__(self, platform, with_memtest=False):
 		MiniSoC.__init__(self, platform, with_memtest)
 		pads_vga, pads_dvi = _get_vga_dvi(platform)
 		self.submodules.fb = framebuffer.Framebuffer(pads_vga, pads_dvi, self.lasmixbar.get_master())
+		_add_vga_tig(platform, self.fb)
 
 class VideomixerSoC(MiniSoC):
-	def __init__(self, platform, with_memtest):
+	def __init__(self, platform, with_memtest=False):
 		MiniSoC.__init__(self, platform, with_memtest)
 		pads_vga, pads_dvi = _get_vga_dvi(platform)
 		self.submodules.fb = framebuffer.MixFramebuffer(pads_vga, pads_dvi,
 			self.lasmixbar.get_master(), self.lasmixbar.get_master())
+		_add_vga_tig(platform, self.fb)
 		self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), self.lasmixbar.get_master())
 		self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), self.lasmixbar.get_master())
 
-SoC = VideomixerSoC
+def get_default_subtarget(platform):
+	if platform.name == "mixxeo":
+		return VideomixerSoC
+	else:
+		return FramebufferSoC