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targets/genesys2: update self.register_sdram

This commit is contained in:
Florent Kermarrec 2020-01-13 14:39:45 +01:00
parent 39ce39a298
commit fe14b9cf86
1 changed files with 3 additions and 1 deletions
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4
litex/boards/targets/genesys2.py
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@ -61,7 +61,9 @@ class BaseSoC(SoCSDRAM):
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy") self.add_csr("ddrphy")
sdram_module = MT41J256M16(self.clk_freq, "1:4") sdram_module = MT41J256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) self.register_sdram(self.ddrphy,
geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings)
# EthernetSoC -------------------------------------------------------------------------------------- # EthernetSoC --------------------------------------------------------------------------------------