merge migen ee0e709 changes
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@ -19,7 +19,8 @@ class MultiRegImpl(Module):
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self.odomain = odomain
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w, signed = value_bits_sign(self.i)
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self.regs = [Signal((w, signed)) for i in range(n)]
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self.regs = [Signal((w, signed), reset_less=True)
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for i in range(n)]
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###
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@ -67,9 +68,9 @@ class PulseSynchronizer(Module):
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###
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toggle_i = Signal()
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toggle_o = Signal()
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toggle_o_r = Signal()
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toggle_i = Signal(reset_less=True)
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toggle_o = Signal() # registered reset_less by MultiReg
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toggle_o_r = Signal(reset_less=True)
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sync_i = getattr(self.sync, idomain)
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sync_o = getattr(self.sync, odomain)
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@ -88,7 +89,7 @@ class BusSynchronizer(Module):
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``MultiReg``)."""
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def __init__(self, width, idomain, odomain, timeout=128):
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self.i = Signal(width)
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self.o = Signal(width)
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self.o = Signal(width, reset_less=True)
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if width == 1:
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self.specials += MultiReg(self.i, self.o, odomain)
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@ -108,8 +109,8 @@ class BusSynchronizer(Module):
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self._pong.i.eq(self._ping.i)
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]
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ibuffer = Signal(width)
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obuffer = Signal(width)
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ibuffer = Signal(width, reset_less=True)
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obuffer = Signal(width) # registered reset_less by MultiReg
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sync_i += If(self._pong.o, ibuffer.eq(self.i))
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ibuffer.attr.add("no_retiming")
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self.specials += MultiReg(ibuffer, obuffer, odomain)
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@ -143,7 +144,7 @@ class GrayCounter(Module):
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class GrayDecoder(Module):
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def __init__(self, width):
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self.i = Signal(width)
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self.o = Signal(width)
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self.o = Signal(width, reset_less=True)
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# # #
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@ -206,7 +207,7 @@ def lcm(a, b):
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class Gearbox(Module):
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def __init__(self, iwidth, idomain, owidth, odomain):
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self.i = Signal(iwidth)
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self.o = Signal(owidth)
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self.o = Signal(owidth, reset_less=True)
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# # #
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@ -224,7 +225,7 @@ class Gearbox(Module):
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]
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self.clock_domains += cd_write, cd_read
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storage = Signal(2*lcm(iwidth, owidth))
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storage = Signal(2*lcm(iwidth, owidth), reset_less=True)
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wrchunks = len(storage)//iwidth
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rdchunks = len(storage)//owidth
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wrpointer = Signal(max=wrchunks, reset=0 if iwidth > owidth else wrchunks//2)
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