dvisampler/dma: reverse slot allocation order
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@ -46,7 +46,7 @@ class _SlotArray(Module, AutoCSR):
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change_slot = Signal()
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current_slot = Signal(max=nslots)
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self.sync += If(change_slot, [If(slot.address_valid, current_slot.eq(n)) for n, slot in enumerate(slots)])
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self.sync += If(change_slot, [If(slot.address_valid, current_slot.eq(n)) for n, slot in reversed(list(enumerate(slots)))])
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self.comb += change_slot.eq(~self.address_valid | self.address_done)
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self.comb += [
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