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soc/cores/clock/intel: speed up PLL config computation

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Caching the list of clock divisors to test speeds up computation by
about a factor of three.
This commit is contained in:
Thomas Watson 2022-10-01 13:04:16 -05:00
parent b7ef989963
commit fea73d932e
1 changed files with 2 additions and 1 deletions
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3
litex/soc/cores/clock/intel_common.py
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@ -59,6 +59,7 @@ class IntelClocking(Module, AutoCSR):
def compute_config(self): def compute_config(self):
valid_configs = {} valid_configs = {}
clkdiv_range_list = list(clkdiv_range(*self.c_div_range)) # for speed
# Only test values of N (input clock divisor) which result in a PFD # Only test values of N (input clock divisor) which result in a PFD
# input frequency within the allowable range. # input frequency within the allowable range.
min_n = math.ceil(self.clkin_freq/self.clkin_pfd_freq_range[1]) min_n = math.ceil(self.clkin_freq/self.clkin_pfd_freq_range[1])
@ -81,7 +82,7 @@ class IntelClocking(Module, AutoCSR):
# For each C, see if the output frequency is within margin # For each C, see if the output frequency is within margin
# and the difference is better than the previous valid, best C. # and the difference is better than the previous valid, best C.
best_diff = float("inf") best_diff = float("inf")
for c in clkdiv_range(*self.c_div_range): for c in clkdiv_range_list:
clk_freq = vco_freq/c clk_freq = vco_freq/c
diff = abs(clk_freq - f) diff = abs(clk_freq - f)
if diff <= f*_m and diff < best_diff: if diff <= f*_m and diff < best_diff: