build/efinix/ifacewriter: PLL/LVDS serdes: Trion support
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@ -278,9 +278,18 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
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if block["input_clock"] == "LVDS_RX":
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if block["version"] == "V3":
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cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="EXTERNAL", refclk_name="{}", ext_refclk_no="{}", ext_refclk_type="LVDS_RX")\n\n' \
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.format(name, block["resource"], block["input_clock_pad"], block["clock_no"])
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cmd += 'design.set_property("{}","FEEDBACK_MODE","CORE","PLL")\n\n'.format(name)
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else:
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cmd += 'design.set_property("{}","EXT_CLK","EXT_CLK{}","PLL")\n'.format(name, block["clock_no"])
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# FIXME: pll feedback
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cmd += 'design.set_property("{}","FEEDBACK_MODE","INTERNAL","PLL")\n'.format(name)
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cmd += 'design.assign_resource("{}","{}","PLL")\n'.format(name, block["resource"])
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elif block["input_clock"] == "EXTERNAL":
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# PLL V1 has a different configuration
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if partnumber[0:2] in ["T4", "T8"]:
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@ -410,13 +419,12 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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cmd.append('design.set_property("{}", "TX_DIFF_TYPE", "LVDS", "{}")'.format(name, block_type))
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cmd.append('design.set_property("{}", "TX_HALF_RATE", "{}", "{}")'.format(name, half_rate, block_type))
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cmd.append('design.set_property("{}", "TX_PRE_EMP", "MEDIUM_LOW", "{}")'.format(name, block_type))
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cmd.append('design.set_property("{}", "TX_SER", "{}", "{}")'.format(name, size, block_type))
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cmd.append('design.set_property("{}", "TX_VOD", "TYPICAL", "{}")'.format(name, block_type))
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else:
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cmd.append('design.set_property("{}","TX_OUTPUT_LOAD","3","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","TX_REDUCED_SWING","0","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","TX_SLOWCLK_DIV","1","{}")'.format(name, block_type))
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#cmd.append('design.set_property("{}","TX_EN_SER","0","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}", "TX_SER", "{}", "{}")'.format(name, size, block_type))
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cmd.append('design.set_property("{}", "TX_EN_SER", "{}", "{}")'.format(name, serdes, block_type))
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cmd.append('design.set_property("{}", "TX_FASTCLK_PIN", "{}", "{}")'.format(name, fast_clk, block_type))
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cmd.append('design.set_property("{}", "TX_MODE", "{}", "{}")'.format(name, tx_mode, block_type))
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@ -461,7 +469,6 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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cmd.append('design.set_property("{}","RX_FIFO","0","{}")'.format(name, block_type))
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cmd.append('design.set_property("{}","RX_HALF_RATE","{}","{}")'.format(name, half_rate, block_type))
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cmd.append('design.set_property("{}","RX_ENA_PIN","{}","{}")'.format(name, ena, block_type))
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cmd.append('design.set_property("{}","RX_DESER","{}","{}")'.format(name, size, block_type))
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cmd.append('design.set_property("{}","RX_DELAY_MODE","{}","{}")'.format(name, rx_delay, block_type))
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cmd.append('design.set_property("{}","RX_DLY_ENA_PIN","{}","{}")'.format(name, delay_ena, block_type))
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cmd.append('design.set_property("{}","RX_DLY_INC_PIN","{}","{}")'.format(name, delay_inc, block_type))
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@ -472,9 +479,11 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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#cmd.append('design.set_property("{}","RX_FIFO_RD_PIN","lvds_rx_inst1_RX_FIFO_RD","{}")'.format(name, block_type))
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#cmd.append('design.set_property("{}","RX_LOCK_PIN","lvds_rx_inst1_RX_LOCK","{}")'.format(name, block_type))
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else:
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rx_delay = "0" if rx_delay == "STATIC" else "1"
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rx_delay = "0"
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cmd.append('design.set_property("{}","RX_EN_DELAY","{}","{}")'.format(name, rx_delay, block_type))
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if not (self.platform.family == "Trion" and serdes == 0):
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cmd.append('design.set_property("{}","RX_DESER","{}","{}")'.format(name, size, block_type))
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cmd.append('design.set_property("{}","RX_CONN_TYPE","{}","{}")'.format(name, rx_mode, block_type))
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cmd.append('design.set_property("{}","RX_DELAY","{}","{}")'.format(name, delay, block_type))
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cmd.append('design.set_property("{}","RX_EN_DESER","{}","{}")'.format(name, serdes, block_type))
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