add PacketBuffer, simplify architecture and reduce ressource usage
This commit is contained in:
Florent Kermarrec
parent
ebf1faed5b
commit
ff0c8e3d22
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@ -6,14 +6,14 @@ from litesata.frontend import *
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from migen.bank.description import *
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class LiteSATA(Module, AutoCSR):
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def __init__(self, phy,
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def __init__(self, phy, buffer_depth=2*fis_max_dwords,
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with_crossbar=False,
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with_bist=False, with_bist_csr=False):
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# phy
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self.phy = phy
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# core
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self.core = LiteSATACore(self.phy)
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self.core = LiteSATACore(self.phy, buffer_depth)
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# frontend
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if with_crossbar:
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@ -301,3 +301,79 @@ class BufferizeEndpoints(Module):
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def __dir__(self):
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return dir(self.submodule)
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class EndpointPacketStatus(Module):
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def __init__(self, endpoint):
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self.start = Signal()
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self.done = Signal()
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self.ongoing = Signal()
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ongoing = Signal()
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self.comb += [
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self.start.eq(endpoint.stb & endpoint.sop & endpoint.ack),
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self.done.eq(endpoint.stb & endpoint.eop & endpoint.ack)
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]
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self.sync += \
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If(self.start,
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ongoing.eq(1)
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).Elif(self.done,
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ongoing.eq(0)
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)
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self.comb += self.ongoing.eq((self.start | ongoing) & ~self.done)
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class PacketBuffer(Module):
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def __init__(self, description, data_depth, cmd_depth=4, almost_full=None):
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self.sink = sink = Sink(description)
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self.source = source = Source(description)
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###
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sink_status = EndpointPacketStatus(self.sink)
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source_status = EndpointPacketStatus(self.source)
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self.submodules += sink_status, source_status
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# store incoming packets
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# cmds
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def cmd_description():
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layout = [("error", 1)]
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return EndpointDescription(layout)
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self.cmd_fifo = cmd_fifo = SyncFIFO(cmd_description(), cmd_depth)
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self.comb += [
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cmd_fifo.sink.stb.eq(sink_status.done),
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cmd_fifo.sink.error.eq(sink.error)
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]
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# data
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self.data_fifo = data_fifo = SyncFIFO(description, data_depth, buffered=True)
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self.comb += [
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Record.connect(self.sink, data_fifo.sink),
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data_fifo.sink.stb.eq(self.sink.stb & cmd_fifo.sink.ack),
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self.sink.ack.eq(data_fifo.sink.ack & cmd_fifo.sink.ack),
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]
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# output packets
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(cmd_fifo.source.stb,
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NextState("SEEK_SOP")
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)
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)
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fsm.act("SEEK_SOP",
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If(~data_fifo.source.sop,
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data_fifo.source.ack.eq(1)
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).Else(
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NextState("OUTPUT")
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)
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)
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fsm.act("OUTPUT",
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Record.connect(data_fifo.source, self.source),
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self.source.error.eq(cmd_fifo.source.error),
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If(source_status.done,
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cmd_fifo.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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# compute almost full
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if almost_full is not None:
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self.almost_full = Signal()
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self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full)
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@ -4,8 +4,8 @@ from litesata.core.transport import LiteSATATransport
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from litesata.core.command import LiteSATACommand
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class LiteSATACore(Module):
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def __init__(self, phy):
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self.link = LiteSATALink(phy)
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def __init__(self, phy, buffer_depth):
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self.link = LiteSATALink(phy, buffer_depth)
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self.transport = LiteSATATransport(self.link)
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self.command = LiteSATACommand(self.transport)
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self.sink, self.source = self.command.sink, self.command.source
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@ -62,6 +62,7 @@ class LiteSATACommandTX(Module):
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If(is_write,
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NextState("WAIT_DMA_ACTIVATE")
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).Else(
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sink.ack.eq(1),
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NextState("IDLE")
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)
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)
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@ -121,11 +122,6 @@ class LiteSATACommandRX(Module):
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###
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cmd_buffer = Buffer(command_rx_cmd_description(32))
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cmd_buffer.sink, cmd_buffer.source = cmd_buffer.d, cmd_buffer.q
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data_buffer = InsertReset(SyncFIFO(command_rx_data_description(32), fis_max_dwords, buffered=True))
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self.submodules += cmd_buffer, data_buffer
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def test_type(name):
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return transport.source.type == fis_types[name]
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@ -151,11 +147,22 @@ class LiteSATACommandRX(Module):
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d2h_error.eq(1)
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)
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read_error = Signal()
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clr_read_error = Signal()
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set_read_error = Signal()
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self.sync += \
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If(clr_read_error,
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read_error.eq(0)
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).Elif(set_read_error,
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read_error.eq(1)
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)
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.dwords_counter.reset.eq(1),
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transport.source.ack.eq(1),
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clr_d2h_error.eq(1),
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clr_read_error.eq(1),
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If(from_tx.write,
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NextState("WAIT_WRITE_ACTIVATE_OR_REG_D2H")
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).Elif(from_tx.read,
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@ -180,12 +187,14 @@ class LiteSATACommandRX(Module):
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)
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)
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fsm.act("PRESENT_WRITE_RESPONSE",
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cmd_buffer.sink.stb.eq(1),
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cmd_buffer.sink.write.eq(1),
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cmd_buffer.sink.last.eq(1),
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cmd_buffer.sink.success.eq(~transport.source.error & ~d2h_error),
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cmd_buffer.sink.failed.eq(transport.source.error | d2h_error),
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If(cmd_buffer.sink.stb & cmd_buffer.sink.ack,
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(1),
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source.write.eq(1),
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source.last.eq(1),
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source.success.eq(~transport.source.error & ~d2h_error),
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source.failed.eq(transport.source.error | d2h_error),
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If(source.stb & source.ack,
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NextState("IDLE")
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)
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)
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@ -196,7 +205,6 @@ class LiteSATACommandRX(Module):
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If(test_type("DATA"),
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NextState("PRESENT_READ_DATA")
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).Elif(test_type("REG_D2H"),
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set_d2h_error.eq(transport.source.status[reg_d2h_status["err"]]),
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NextState("PRESENT_READ_RESPONSE")
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)
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)
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@ -217,90 +225,39 @@ class LiteSATACommandRX(Module):
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)
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)
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self.comb += [
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data_buffer.sink.sop.eq(transport.source.sop),
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data_buffer.sink.eop.eq(transport.source.eop),
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data_buffer.sink.data.eq(transport.source.data)
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]
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fsm.act("PRESENT_READ_DATA",
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data_buffer.sink.stb.eq(transport.source.stb),
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transport.source.ack.eq(data_buffer.sink.ack),
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If(data_buffer.sink.stb & data_buffer.sink.ack,
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set_read_error.eq(transport.source.error),
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source.stb.eq(transport.source.stb),
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source.sop.eq(transport.source.sop),
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source.eop.eq(transport.source.eop),
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source.read.eq(~is_identify),
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source.identify.eq(is_identify),
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source.success.eq(~transport.source.error),
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source.failed.eq(transport.source.error),
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source.last.eq(is_identify),
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source.data.eq(transport.source.data),
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transport.source.ack.eq(source.ack),
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If(source.stb & source.ack,
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self.dwords_counter.ce.eq(~read_done),
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If(data_buffer.sink.eop,
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If(read_done & ~is_identify,
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NextState("WAIT_READ_DATA_OR_REG_D2H")
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If(source.eop,
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If(is_identify,
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NextState("IDLE")
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).Else(
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NextState("PRESENT_READ_RESPONSE")
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NextState("WAIT_READ_DATA_OR_REG_D2H")
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)
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)
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)
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)
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read_error = Signal()
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self.sync += \
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If(fsm.before_entering("PRESENT_READ_DATA"),
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read_error.eq(1)
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).Elif(transport.source.stb & transport.source.ack & transport.source.eop,
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read_error.eq(transport.source.error)
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)
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fsm.act("PRESENT_READ_RESPONSE",
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cmd_buffer.sink.stb.eq(1),
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cmd_buffer.sink.read.eq(~is_identify),
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cmd_buffer.sink.identify.eq(is_identify),
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cmd_buffer.sink.last.eq(read_done | is_identify),
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cmd_buffer.sink.success.eq(~read_error & ~d2h_error),
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cmd_buffer.sink.failed.eq(read_error | d2h_error),
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If(cmd_buffer.sink.stb & cmd_buffer.sink.ack,
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If(cmd_buffer.sink.failed,
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data_buffer.reset.eq(1)
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),
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If(read_done | is_identify,
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NextState("IDLE")
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).Else(
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NextState("WAIT_READ_DATA_OR_REG_D2H")
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)
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)
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)
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self.out_fsm = out_fsm = FSM(reset_state="IDLE")
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out_fsm.act("IDLE",
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If(cmd_buffer.source.stb,
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If((cmd_buffer.source.read | cmd_buffer.source.identify) & cmd_buffer.source.success,
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NextState("PRESENT_RESPONSE_WITH_DATA"),
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).Else(
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NextState("PRESENT_RESPONSE_WITHOUT_DATA"),
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)
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)
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)
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self.comb += [
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source.write.eq(cmd_buffer.source.write),
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source.read.eq(cmd_buffer.source.read),
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source.identify.eq(cmd_buffer.source.identify),
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source.last.eq(cmd_buffer.source.last),
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source.success.eq(cmd_buffer.source.success),
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source.failed.eq(cmd_buffer.source.failed),
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source.data.eq(data_buffer.source.data)
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]
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out_fsm.act("PRESENT_RESPONSE_WITH_DATA",
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source.stb.eq(data_buffer.source.stb),
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source.sop.eq(data_buffer.source.sop),
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source.eop.eq(data_buffer.source.eop),
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data_buffer.source.ack.eq(source.ack),
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If(source.stb & source.eop & source.ack,
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cmd_buffer.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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out_fsm.act("PRESENT_RESPONSE_WITHOUT_DATA",
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(1),
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source.read.eq(1),
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source.last.eq(1),
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source.success.eq(read_done & ~read_error & ~d2h_error),
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source.failed.eq(~read_done | read_error | d2h_error),
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If(source.stb & source.ack,
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cmd_buffer.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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@ -110,6 +110,7 @@ class LiteSATALinkTX(Module):
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class LiteSATALinkRX(Module):
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def __init__(self, phy):
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self.source = Source(link_description(32))
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self.hold = Signal()
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self.to_tx = Source(from_rx)
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###
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@ -152,15 +153,11 @@ class LiteSATALinkRX(Module):
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crc_error.eq(crc.source.error)
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)
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# small fifo to manage HOLD
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self.fifo = SyncFIFO(link_description(32), 32)
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# graph
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self.comb += [
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cont.source.ack.eq(1),
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Record.connect(scrambler.source, crc.sink),
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Record.connect(crc.source, self.fifo.sink),
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Record.connect(self.fifo.source, self.source)
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Record.connect(crc.source, self.source),
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]
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cont_source_data_d = Signal(32)
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self.sync += \
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@ -198,7 +195,7 @@ class LiteSATALinkRX(Module):
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insert.eq(primitives["HOLDA"])
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).Elif(det == primitives["EOF"],
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NextState("WTRM")
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).Elif(self.fifo.fifo.level > 8,
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).Elif(self.hold,
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insert.eq(primitives["HOLD"])
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)
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)
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@ -237,8 +234,15 @@ class LiteSATALinkRX(Module):
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]
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class LiteSATALink(Module):
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def __init__(self, phy):
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def __init__(self, phy, buffer_depth):
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self.tx_buffer = PacketBuffer(link_description(32), buffer_depth)
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self.tx = LiteSATALinkTX(phy)
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self.rx = LiteSATALinkRX(phy)
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self.comb += Record.connect(self.rx.to_tx, self.tx.from_rx)
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self.sink, self.source = self.tx.sink, self.rx.source
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self.rx_buffer = PacketBuffer(link_description(32), buffer_depth, almost_full=3*buffer_depth//4)
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self.comb += [
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Record.connect(self.tx_buffer.source, self.tx.sink),
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Record.connect(self.rx.to_tx, self.tx.from_rx),
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Record.connect(self.rx.source, self.rx_buffer.sink),
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self.rx.hold.eq(self.rx_buffer.almost_full)
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]
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self.sink, self.source = self.tx_buffer.sink, self.rx_buffer.source
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@ -128,7 +128,7 @@ class LiteSATABISTChecker(Module):
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If(sink.stb,
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counter.ce.eq(1),
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If(sink.data != expected_data,
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self.error_counter.ce.eq(1)
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self.error_counter.ce.eq(~sink.last)
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),
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If(sink.eop,
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If(sink.last,
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@ -59,7 +59,7 @@ class TB(Module):
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link_debug=False, link_random_level=50,
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transport_debug=False, transport_loopback=False,
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hdd_debug=True)
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self.core = LiteSATACore(self.hdd.phy)
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self.core = LiteSATACore(self.hdd.phy, buffer_depth=512)
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self.streamer = CommandStreamer()
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self.streamer_randomizer = Randomizer(command_tx_description(32), level=50)
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@ -17,7 +17,7 @@ class TB(Module):
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self.hdd = HDD(
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link_debug=False, link_random_level=50,
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transport_debug=False, transport_loopback=True)
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self.link = InsertReset(LiteSATALink(self.hdd.phy))
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self.link = InsertReset(LiteSATALink(self.hdd.phy, buffer_depth=512))
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self.streamer = LinkStreamer()
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self.streamer_randomizer = Randomizer(link_description(32), level=50)
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@ -202,7 +202,7 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
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self.mila = MiLa(depth=2048, dat=Cat(*debug))
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self.mila.add_port(Term)
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if export_mila:
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mila_filename = os.path.join(platform.soc_ext_path, "test", "mila.csv")
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mila_filename = os.path.join("test", "mila.csv")
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self.mila.export(self, debug, mila_filename)
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def do_finalize(self):
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@ -18,27 +18,27 @@ if len(sys.argv) < 2:
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conditions = {}
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conditions["wr_cmd"] = {
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"bistsocdevel_core_sink_stb" : 1,
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"bistsocdevel_core_sink_payload_write" : 1,
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"sata_command_tx_sink_stb" : 1,
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"sata_command_tx_sink_payload_write" : 1,
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}
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conditions["wr_dma_activate"] = {
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"bistsocdevel_core_source_source_stb" : 1,
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"bistsocdevel_core_source_source_payload_write" : 1,
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"sata_command_rx_source_stb" : 1,
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"sata_command_rx_source_payload_write" : 1,
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}
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conditions["rd_cmd"] = {
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"bistsocdevel_core_sink_stb" : 1,
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"bistsocdevel_core_sink_payload_read" : 1,
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"sata_command_tx_sink_stb" : 1,
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"sata_command_tx_sink_payload_read" : 1,
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}
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conditions["rd_data"] = {
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"bistsocdevel_core_source_source_stb" : 1,
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"bistsocdevel_core_source_source_payload_read" : 1,
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"sata_command_rx_source_stb" : 1,
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"sata_command_rx_source_payload_read" : 1,
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}
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||||
conditions["id_cmd"] = {
|
||||
"bistsocdevel_core_sink_stb" : 1,
|
||||
"bistsocdevel_core_sink_payload_identify" : 1,
|
||||
"sata_command_tx_sink_stb" : 1,
|
||||
"sata_command_tx_sink_payload_identify" : 1,
|
||||
}
|
||||
conditions["id_pio_setup"] = {
|
||||
"bistsocdevel_source_source_payload_data" : primitives["X_RDY"],
|
||||
"source_source_payload_data" : primitives["X_RDY"],
|
||||
}
|
||||
|
||||
mila.prog_term(port=0, cond=conditions[sys.argv[1]])
|
||||
|
|
@ -47,9 +47,9 @@ mila.prog_sum("term")
|
|||
# Trigger / wait / receive
|
||||
mila.trigger(offset=512, length=2000)
|
||||
|
||||
identify.run()
|
||||
#identify.run()
|
||||
generator.run(0, 2, 0)
|
||||
checker.run(0, 2, 0)
|
||||
#checker.run(0, 2, 0)
|
||||
mila.wait_done()
|
||||
|
||||
mila.read()
|
||||
|
|
@ -57,7 +57,10 @@ mila.export("dump.vcd")
|
|||
###
|
||||
wb.close()
|
||||
|
||||
print_link_trace(mila,
|
||||
tx_data_name="bistsocdevel_sink_sink_payload_data",
|
||||
rx_data_name="bistsocdevel_source_source_payload_data"
|
||||
f = open("dump_link.txt", "w")
|
||||
data = link_trace(mila,
|
||||
tx_data_name="sink_sink_payload_data",
|
||||
rx_data_name="source_source_payload_data"
|
||||
)
|
||||
f.write(data)
|
||||
f.close()
|
||||
|
|
|
|||
Loading…
Reference in New Issue