migen/genlib/io: add DifferentialOutput and Xilinx implementation

mibuild/xilinx/common.py

@@ -92,6 +92,15 @@ class XilinxDifferentialInput:
 	def lower(dr):
 		return XilinxDifferentialInputImpl(dr.i_p, dr.i_n, dr.o)
 
+class XilinxDifferentialOutputImpl(Module):
+	def __init__(self, i, o_p, o_n):
+		self.specials += Instance("OBUFDS", i_I=i, o_O=o_p, o_OB=o_n)
+
+class XilinxDifferentialOutput:
+	@staticmethod
+	def lower(dr):
+		return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
+
 class XilinxGenericPlatform(GenericPlatform):
 	bitstream_ext = ".bit"
 
@@ -101,6 +110,7 @@ class XilinxGenericPlatform(GenericPlatform):
 			MultiReg:					XilinxMultiReg,
 			AsyncResetSynchronizer:		XilinxAsyncResetSynchronizer,
 			DifferentialInput:			XilinxDifferentialInput,
+			DifferentialOutput:			XilinxDifferentialOutput,
 		}
 		so.update(special_overrides)
 		return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)

migen/genlib/io.py

@@ -17,3 +17,19 @@ class DifferentialInput(Special):
 	@staticmethod
 	def lower(dr):
 		raise NotImplementedError("Attempted to use a differential input, but platform does not support them")
+
+class DifferentialOutput(Special):
+	def __init__(self, i, o_p, o_n):
+		Special.__init__(self)
+		self.i = i
+		self.o_p = o_p
+		self.o_n = o_n
+
+	def iter_expressions(self):
+		yield self, "i", SPECIAL_INPUT
+		yield self, "o_p", SPECIAL_OUTPUT
+		yield self, "o_n", SPECIAL_OUTPUT
+
+	@staticmethod
+	def lower(dr):
+		raise NotImplementedError("Attempted to use a differential output, but platform does not support them")