Merge pull request #321 from gsomlo/gls-rocket-aximem-wide
cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi
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commit
ffa7ca8f0b
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@ -53,6 +53,8 @@ CPU_VARIANTS = {
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"standard": [None, "std"],
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"full": [],
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"linux" : [],
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"linuxd" : [],
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"linuxq" : [],
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}
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CPU_VARIANTS_EXTENSIONS = ["debug", "no-dsp"]
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@ -41,12 +41,16 @@ from litex.soc.cores.cpu import CPU
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CPU_VARIANTS = {
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"standard": "freechips.rocketchip.system.LitexConfig",
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"linux": "freechips.rocketchip.system.LitexLinuxConfig",
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"linuxd": "freechips.rocketchip.system.LitexLinuxDConfig",
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"linuxq": "freechips.rocketchip.system.LitexLinuxQConfig",
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"full": "freechips.rocketchip.system.LitexFullConfig",
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}
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GCC_FLAGS = {
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"standard": "-march=rv64imac -mabi=lp64 ",
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"linux": "-march=rv64imac -mabi=lp64 ",
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"linuxd": "-march=rv64imac -mabi=lp64 ",
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"linuxq": "-march=rv64imac -mabi=lp64 ",
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"full": "-march=rv64imafdc -mabi=lp64 ",
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}
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@ -54,6 +58,8 @@ AXI_DATA_WIDTHS = {
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# variant : (mem, mmio)
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"standard": ( 64, 64),
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"linux": ( 64, 64),
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"linuxd": (128, 64),
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"linuxq": (256, 64),
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"full": ( 64, 64),
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}
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@ -1 +1 @@
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Subproject commit d67a7d7a12ff06297226b1862412849c4d50e949
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Subproject commit fb31001d9655ebfb8ab25209e094939f68feb6a7
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@ -69,10 +69,12 @@ class SoCSDRAM(SoCCore):
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if self.cpu.name == "rocket":
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# Rocket has its own I/D L1 cache: connect directly to LiteDRAM, also bypassing MMIO/CSR wb bus:
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if port.data_width == self.cpu.mem_axi.data_width:
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print("# Matching AXI MEM data width ({})\n".format(port.data_width))
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# straightforward AXI link, no data_width conversion needed:
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self.submodules += LiteDRAMAXI2Native(self.cpu.mem_axi, port,
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base_address=self.mem_map["main_ram"])
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else:
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print("# Converting MEM data width: ram({}) to cpu({}), via Wishbone\n".format(port.data_width, self.cpu.mem_axi.data_width))
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# FIXME: replace WB data-width converter with native AXI converter!!!
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mem_wb = wishbone.Interface(data_width=self.cpu.mem_axi.data_width,
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adr_width=32-log2_int(self.cpu.mem_axi.data_width//8))
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