Merge pull request #1617 from trabucayre/colognechip
build: adding colognechip toolchain
This commit is contained in:
enjoy-digital
GitHub
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from litex.build.colognechip.platform import CologneChipPlatform
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2023 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabubucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import sys
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import math
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import subprocess
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from shutil import which, copyfile
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from migen.fhdl.structure import _Fragment
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from litex.build.generic_platform import *
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from litex.build import tools
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from litex.build.generic_toolchain import GenericToolchain
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from litex.build.yosys_wrapper import YosysWrapper, yosys_args, yosys_argdict
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# CologneChipToolchain -----------------------------------------------------------------------------
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class CologneChipToolchain(GenericToolchain):
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attr_translate = {}
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supported_build_backend = ["litex", "edalize"]
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def __init__(self):
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super().__init__()
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self._yosys = None
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self._yosys_cmds = []
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self._synth_opts = "-nomx8 "
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def finalize(self):
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self._yosys = YosysWrapper(
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platform = self.platform,
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build_name = self._build_name,
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target = "gatemate",
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output_name = self._build_name+"_synth",
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template = [],
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yosys_opts = self._synth_opts,
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yosys_cmds = self._yosys_cmds,
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synth_format = "v",
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)
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# IO Constraints (.ccf) ------------------------------------------------------------------------
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def _get_pin_direction(self, pinname):
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pins = self.platform.constraint_manager.get_io_signals()
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for pin in sorted(pins, key=lambda x: x.duid):
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if (pinname.split("[")[0] == pin.name):
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if pin.direction == "output":
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return "Pin_out"
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elif pin.direction == "input":
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return "Pin_in"
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else:
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return "Pin_inout"
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return "Unknown"
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def build_io_constraints(self):
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ccf = []
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flat_sc = []
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for name, pins, other, resource in self.named_sc:
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if len(pins) > 1:
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for i, p in enumerate(pins):
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flat_sc.append((f"{name}[{i}]", p, other))
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else:
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flat_sc.append((name, pins[0], other))
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for name, pin, other in flat_sc:
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pin_cst = ""
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if pin != "X":
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direction = self._get_pin_direction(name)
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pin_cst = f"{direction} \"{name}\" Loc = \"{pin}\""
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for c in other:
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if isinstance(c, Misc):
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pin_cst += f" | {c.misc}"
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pin_cst += ";"
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ccf.append(pin_cst)
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if self.named_pc:
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ccf.extend(self.named_pc)
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tools.write_to_file(f"{self._build_name}.ccf", "\n".join(ccf))
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return (f"{self._build_name}.ccf", "CCF")
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# Project (.ys) --------------------------------------------------------------------------------
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def build_project(self):
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""" create project files (mainly Yosys ys file)
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"""
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self._yosys.build_script()
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# Script ---------------------------------------------------------------------------------------
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def build_script(self):
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""" create build_xxx.yy by using Yosys and p_r instances.
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Return
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======
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the script name (str)
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"""
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if sys.platform in ("win32", "cygwin"):
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script_ext = ".bat"
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script_contents = "@echo off\nrem Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n\n"
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fail_stmt = " || exit /b"
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else:
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script_ext = ".sh"
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script_contents = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\nset -e\n"
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fail_stmt = ""
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fail_stmt += "\n"
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# yosys call
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script_contents += self._yosys.get_yosys_call("script") + fail_stmt
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# p_r call
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script_contents += "p_r -ccf {build_name}.ccf -A 1 -i {build_name}_synth.v -o {build_name} -lib ccag\n".format(
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build_name = self._build_name)
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script_file = "build_" + self._build_name + script_ext
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tools.write_to_file(script_file, script_contents, force_unix=False)
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return script_file
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def run_script(self, script):
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""" run build_xxx.yy script
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Parameters
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==========
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script: str
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script name to use
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"""
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if sys.platform in ("win32", "cygwin"):
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shell = ["cmd", "/c"]
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else:
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shell = ["bash"]
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if which("yosys") is None or which("p_r") is None:
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msg = "Unable to find CologneChip toolchain, please:\n"
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msg += "- Add Yosys/p_r toolchain to your $PATH."
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raise OSError(msg)
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if subprocess.call(shell + [script]) != 0:
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raise OSError("Error occured during Yosys/p_r's script execution.")
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def add_period_constraint(self, platform, clk, period):
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pass
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def colognechip_args(parser):
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# TODO: yosys (default's yosys aren't supported
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# TODO: p_r args
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pass
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def colognechip_argdict(args):
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# TODO: ditto
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return {}
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2023 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen.fhdl.module import Module
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import *
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# CologneChip AsyncResetSynchronizer ---------------------------------------------------------------
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class CologneChipAsyncResetSynchronizerImpl(Module):
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def __init__(self, cd, async_reset):
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rst1 = Signal()
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self.specials += [
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Instance("CC_DFF",
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p_CLK_INV = 0,
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p_EN_INV = 0,
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p_SR_INV = 0,
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p_SR_VAL = 1,
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i_D = 0,
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i_CLK = cd.clk,
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i_EN = 1,
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i_SR = async_reset,
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o_Q = rst1),
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Instance("CC_DFF",
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p_CLK_INV = 0,
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p_EN_INV = 0,
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p_SR_INV = 0,
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p_SR_VAL = 1,
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i_D = rst1,
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i_CLK = cd.clk,
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i_EN = 1,
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i_SR = async_reset,
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o_Q = cd.rst)
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]
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class CologneChipAsyncResetSynchronizer:
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@staticmethod
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def lower(dr):
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return CologneChipAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
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# CologneChip DDR Input ----------------------------------------------------------------------------
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class CologneChipDDRInputImpl(Module):
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def __init__(self, i, o1, o2, clk):
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self.specials += Instance("CC_IDDR",
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i_CLK = clk,
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i_D = i,
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o_Q0 = o1,
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o_Q1 = o2,
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)
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class CologneChipDDRInput:
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@staticmethod
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def lower(dr):
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return CologneChipInputImpl(dr.i, dr.o1, dr.o2, dr.clk)
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# CologneChip DDR Output ---------------------------------------------------------------------------
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class CologneChipDDROutputImpl(Module):
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def __init__(self, i1, i2, o, clk):
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self.specials += Instance("CC_ODDR",
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p_CLK_INV = 0,
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i_CLK = clk,
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i_DDR = ~clk,
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i_D0 = i1,
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i_D1 = i2,
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o_Q = o,
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)
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class CologneChipDDROutput:
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@staticmethod
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def lower(dr):
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return CologneChipDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
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# CologneChip Differential Input -------------------------------------------------------------------
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class CologneChipDifferentialInputImpl(Module):
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def __init__(self, i_p, i_n, o):
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self.specials += Instance("CC_LVDS_IBUF",
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i_I_P = i_p,
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i_I_N = i_n,
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o_Y = o,
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)
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class CologneChipDifferentialInput:
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@staticmethod
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def lower(dr):
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return CologneChipDifferentialInputImpl(dr.i_p, dr.i_n, dr.o)
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# CologneChip Differential Output ------------------------------------------------------------------
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class CologneChipDifferentialOutputImpl(Module):
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def __init__(self, i, o_p, o_n):
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self.specials += Instance("CC_LVDS_OBUF",
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i_A = i,
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o_O_P = o_p,
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o_O_N = o_n,
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)
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class CologneChipDifferentialOutput:
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@staticmethod
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def lower(dr):
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return CologneChipDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
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# CologneChip SDR Input ----------------------------------------------------------------------------
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class CologneChipSDRInputImpl(Module):
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def __init__(self, i, o):
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self.specials += Instance("CC_IBUF",
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i_I = i,
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o_O = o,
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)
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class CologneChipSDRInput:
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@staticmethod
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def lower(dr):
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return CologneChipSDRInput(dr.i, dr.o)
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# CologneChip Special Overrides --------------------------------------------------------------------
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colognechip_special_overrides = {
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AsyncResetSynchronizer: CologneChipAsyncResetSynchronizer,
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DDRInput: CologneChipDDRInput,
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DDROutput: CologneChipDDROutput,
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DifferentialInput: CologneChipDifferentialInput,
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DifferentialOutput: CologneChipDifferentialOutput,
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SDRInput: CologneChipSDRInput,
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}
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2023 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabubucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from litex.build.generic_platform import GenericPlatform
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from litex.build.colognechip import common, colognechip
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# CologneChipPlatform ------------------------------------------------------------------------------
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class CologneChipPlatform(GenericPlatform):
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bitstream_ext = "_00.cfg.bit"
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_supported_toolchains = ["colognechip"]
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def __init__(self, device, *args, toolchain="colognechip", devicename=None, **kwargs):
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GenericPlatform.__init__(self, device, *args, **kwargs)
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self.toolchain = colognechip.CologneChipToolchain()
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def get_verilog(self, *args, special_overrides=dict(), **kwargs):
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so = dict(common.colognechip_special_overrides)
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so.update(special_overrides)
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return GenericPlatform.get_verilog(self, *args,
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special_overrides = so,
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attr_translate = self.toolchain.attr_translate,
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**kwargs)
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def build(self, *args, **kwargs):
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return self.toolchain.build(self, *args, **kwargs)
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def add_period_constraint(self, clk, period):
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if clk is None: return
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self.toolchain.add_period_constraint(self, clk, period)
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@classmethod
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def fill_args(cls, toolchain, parser):
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"""
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pass parser to the specific toolchain to
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fill this with toolchain args
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Parameters
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==========
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toolchain: str
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toolchain name
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parser: argparse.ArgumentParser
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parser to be filled
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"""
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colognechip.colognechip_args(parser)
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@classmethod
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def get_argdict(cls, toolchain, args):
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"""
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return a dict of args
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Parameters
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==========
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toolchain: str
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toolchain name
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Return
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======
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a dict of key/value for each args or an empty dict
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"""
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return colognechip.colognechip_argdict(args)
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