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soc/integration/core: Connect SoCController's reset to CRG.rs do full reset of the SoC with reboot when signals are presents.

This commit is contained in:
Florent Kermarrec 2020-11-04 10:58:00 +01:00
parent 2c504783ca
commit ffc554dede
1 changed files with 6 additions and 0 deletions
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6
litex/soc/integration/soc.py
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@ -914,6 +914,12 @@ class SoC(Module):
"axi-lite": axi.AXILiteInterconnectShared, "axi-lite": axi.AXILiteInterconnectShared,
}[self.bus.standard] }[self.bus.standard]
# SoC Reset --------------------------------------------------------------------------------
# Connect SoCController's reset to CRG's reset if presents.
if hasattr(self, "ctrl") and hasattr(self, "crg"):
if hasattr(self.ctrl, "_reset") and hasattr(self.crg, "rst"):
self.comb += self.crg.rst.eq(self.ctrl._reset.re)
# SoC CSR bridge --------------------------------------------------------------------------- # SoC CSR bridge ---------------------------------------------------------------------------
# FIXME: for now, use registered CSR bridge when SDRAM is present; find the best compromise. # FIXME: for now, use registered CSR bridge when SDRAM is present; find the best compromise.
self.add_csr_bridge(self.mem_map["csr"], register=hasattr(self, "sdram")) self.add_csr_bridge(self.mem_map["csr"], register=hasattr(self, "sdram"))