82 lines
2.9 KiB
Python
Executable File
82 lines
2.9 KiB
Python
Executable File
#!/usr/bin/env python3
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from setuptools import setup
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from setuptools import find_packages
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with open("README.md", "r", encoding="utf-8") as fp:
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long_description = fp.read()
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setup(
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name = "litex",
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version = "2024.08",
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description = "Python SoC/Core builder for building FPGA based systems.",
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long_description = long_description,
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long_description_content_type = "text/markdown",
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author = "Florent Kermarrec",
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author_email = "florent@enjoy-digital.fr",
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url = "http://enjoy-digital.fr",
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download_url = "https://github.com/enjoy-digital/litex",
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test_suite = "test",
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license = "BSD",
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python_requires = "~=3.7",
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install_requires = [
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"migen",
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"packaging",
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"pyserial",
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"requests",
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],
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extras_require = {
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"develop": [
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"meson"
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"pexpect"
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"setuptools"
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"requests"
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]
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},
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packages = find_packages(exclude=("test*", "sim*", "doc*")),
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include_package_data = True,
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package_data = {
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'litex.soc.doc': ['static/*']
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},
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platforms = ["Any"],
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keywords = "HDL ASIC FPGA hardware design",
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classifiers = [
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"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
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"Environment :: Console",
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"Development Status :: 3 - Alpha",
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"Intended Audience :: Developers",
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"License :: OSI Approved :: BSD License",
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"Operating System :: OS Independent",
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"Programming Language :: Python",
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],
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entry_points = {
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"console_scripts": [
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# Terminal/Server/Client.
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"litex_term = litex.tools.litex_term:main",
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"litex_server = litex.tools.litex_server:main",
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"litex_cli = litex.tools.litex_client:main",
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# SoC Generators.
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"litex_soc_gen = litex.tools.litex_soc_gen:main",
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"litex_periph_gen = litex.tools.litex_periph_gen:main",
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# Simulation.
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"litex_sim=litex.tools.litex_sim:main",
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# Demos.
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"litex_bare_metal_demo=litex.soc.software.demo.demo:main",
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# Export tools.
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"litex_json2dts_linux = litex.tools.litex_json2dts_linux:main",
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"litex_json2dts_zephyr = litex.tools.litex_json2dts_zephyr:main",
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"litex_json2renode = litex.tools.litex_json2renode:main",
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# Development tools.
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"litex_read_verilog = litex.tools.litex_read_verilog:main",
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"litex_contributors = litex.tools.litex_contributors:main",
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],
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},
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)
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