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018afe57ef
litex
/
migen
History
Sebastien Bourdeauducq
018afe57ef
genlib/record: support passing params in same object
2013-10-21 22:05:28 +02:00
..
actorlib
actorlib/fifo: do not duplicate safe write logic
2013-09-04 17:33:53 +02:00
bank
bank/csrgen: add get_offset function to pre-calculate register addresses
2013-08-02 23:05:54 +02:00
bus
bus/wb2lasmi: use existing interface to determine WB width to be consistent with other modules
2013-08-26 20:33:34 +02:00
fhdl
add ternary operator sel ? a : b
2013-08-12 13:15:56 +02:00
flow
flow/actor/PipelinedActor: clean up
2013-07-12 18:52:34 +02:00
genlib
genlib/record: support passing params in same object
2013-10-21 22:05:28 +02:00
graph
treeviz: support multiline labels
2013-08-07 21:46:03 +02:00
pytholite
pytholite/io: len -> flen
2013-07-27 15:38:48 +02:00
sim
fhdl: do not export Fragment
2013-07-25 18:52:54 +02:00
__init__.py
Initial import, FHDL basic structure, divider example
2011-12-04 16:44:38 +01:00