133 lines
3.9 KiB
Python
133 lines
3.9 KiB
Python
from migen import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.fifo import _inc
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from migen.genlib.record import Record, layout_len
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from migen.genlib.misc import optree
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from migen.bank.description import *
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from misoc.video.dvisampler.common import channel_layout
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class _SyncBuffer(Module):
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def __init__(self, width, depth):
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self.din = Signal(width)
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self.dout = Signal(width)
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self.re = Signal()
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###
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produce = Signal(max=depth)
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consume = Signal(max=depth)
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storage = Memory(width, depth)
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self.specials += storage
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wrport = storage.get_port(write_capable=True)
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self.specials += wrport
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self.comb += [
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wrport.adr.eq(produce),
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wrport.dat_w.eq(self.din),
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wrport.we.eq(1)
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]
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self.sync += _inc(produce, depth)
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rdport = storage.get_port(async_read=True)
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self.specials += rdport
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self.comb += [
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rdport.adr.eq(consume),
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self.dout.eq(rdport.dat_r)
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]
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self.sync += If(self.re, _inc(consume, depth))
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class ChanSync(Module, AutoCSR):
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def __init__(self, nchan=3, depth=8):
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self.valid_i = Signal()
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self.chan_synced = Signal()
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self._channels_synced = CSRStatus()
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lst_control = []
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all_control = Signal()
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for i in range(nchan):
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name = "data_in" + str(i)
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data_in = Record(channel_layout, name=name)
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setattr(self, name, data_in)
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name = "data_out" + str(i)
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data_out = Record(channel_layout, name=name)
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setattr(self, name, data_out)
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###
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syncbuffer = RenameClockDomains(_SyncBuffer(layout_len(channel_layout), depth), "pix")
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self.submodules += syncbuffer
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self.comb += [
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syncbuffer.din.eq(data_in.raw_bits()),
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data_out.raw_bits().eq(syncbuffer.dout)
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]
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is_control = Signal()
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self.comb += [
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is_control.eq(~data_out.de),
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syncbuffer.re.eq(~is_control | all_control)
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]
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lst_control.append(is_control)
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some_control = Signal()
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self.comb += [
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all_control.eq(optree("&", lst_control)),
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some_control.eq(optree("|", lst_control))
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]
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self.sync.pix += If(~self.valid_i,
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self.chan_synced.eq(0)
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).Else(
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If(some_control,
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If(all_control,
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self.chan_synced.eq(1)
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).Else(
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self.chan_synced.eq(0)
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)
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)
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)
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self.specials += MultiReg(self.chan_synced, self._channels_synced.status)
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class _TB(Module):
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def __init__(self, test_seq_it):
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self.test_seq_it = test_seq_it
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self.submodules.chansync = RenameClockDomains(ChanSync(), {"pix": "sys"})
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self.comb += self.chansync.valid_i.eq(1)
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def do_simulation(self, selfp):
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try:
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de0, de1, de2 = next(self.test_seq_it)
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except StopIteration:
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raise StopSimulation
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selfp.chansync.data_in0.de = de0
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selfp.chansync.data_in1.de = de1
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selfp.chansync.data_in2.de = de2
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selfp.chansync.data_in0.d = selfp.simulator.cycle_counter
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selfp.chansync.data_in1.d = selfp.simulator.cycle_counter
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selfp.chansync.data_in2.d = selfp.simulator.cycle_counter
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out0 = selfp.chansync.data_out0.d
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out1 = selfp.chansync.data_out1.d
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out2 = selfp.chansync.data_out2.d
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print("{0:5} {1:5} {2:5}".format(out0, out1, out2))
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if __name__ == "__main__":
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from migen.sim.generic import run_simulation
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test_seq = [
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(1, 1, 1),
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(1, 1, 0),
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(0, 0, 0),
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(0, 0, 0),
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(0, 0, 1),
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(1, 1, 1),
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(1, 1, 1),
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]
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tb = _TB(iter(test_seq*2))
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run_simulation(tb)
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