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8aa3fb3eb7
Since ressource usage is low with default depth of 16 (implemented in RAM LUTs) we don't keep old behaviour. Tested successfully with BIOS and flterm.
47 lines
1.5 KiB
Python
47 lines
1.5 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.bank.eventmanager import *
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from migen.genlib.record import Record
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from migen.flow.actor import Sink, Source
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from migen.actorlib.fifo import SyncFIFO
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class UART(Module, AutoCSR):
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def __init__(self, phy,
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tx_fifo_depth=16,
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rx_fifo_depth=16):
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self._rxtx = CSR(8)
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self._txfull = CSRStatus()
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self._rxempty = CSRStatus()
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self.submodules.ev = EventManager()
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self.ev.tx = EventSourceProcess()
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self.ev.rx = EventSourceProcess()
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self.ev.finalize()
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# # #
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tx_fifo = SyncFIFO([("data", 8)], tx_fifo_depth)
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self.submodules += tx_fifo
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self.comb += [
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tx_fifo.sink.stb.eq(self._rxtx.re),
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tx_fifo.sink.data.eq(self._rxtx.r),
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self._txfull.status.eq(~tx_fifo.sink.ack),
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Record.connect(tx_fifo.source, phy.sink)
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]
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rx_fifo = SyncFIFO([("data", 8)], rx_fifo_depth)
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self.submodules += rx_fifo
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self.comb += [
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Record.connect(phy.source, rx_fifo.sink),
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self._rxempty.status.eq(~rx_fifo.source.stb),
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self._rxtx.w.eq(rx_fifo.source.data),
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rx_fifo.source.ack.eq(self.ev.rx.clear)
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]
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self.comb += [
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# Generate TX IRQ when tx_fifo becomes empty
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self.ev.tx.trigger.eq(tx_fifo.source.stb),
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# Generate RX IRQ when rx_fifo becomes non-empty
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self.ev.rx.trigger.eq(~rx_fifo.source.stb),
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]
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