133 lines
3.7 KiB
Python
133 lines
3.7 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoclib import sdram, spiflash
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from misoclib.sdram.phy import k7ddrphy
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from misoclib.gensoc import SDRAMSoC
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from extcores import *
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from liteeth.phy.gmii import LiteEthPHYGMII
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from liteeth.mac import LiteEthMAC
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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clk200 = platform.request("clk200")
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clk200_se = Signal()
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self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys = Signal()
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pll_sys4x = Signal()
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pll_clk200 = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
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p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 125MHz
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p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
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# 500MHz
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p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_sys4x,
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# 200MHz
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p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=pll_clk200,
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p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
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p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
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),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
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Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
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AsyncResetSynchronizer(self.cd_clk200, ~pll_locked),
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]
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reset_counter = Signal(4, reset=15)
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ic_reset = Signal(reset=1)
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self.sync.clk200 += \
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If(reset_counter != 0,
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reset_counter.eq(reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
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class BaseSoC(SDRAMSoC):
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default_platform = "kc705"
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csr_map = {
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"spiflash": 10,
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"ddrphy": 11,
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}
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csr_map.update(SDRAMSoC.csr_map)
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def __init__(self, platform, **kwargs):
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SDRAMSoC.__init__(self, platform,
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clk_freq=125*1000000, cpu_reset_address=0xaf0000,
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**kwargs)
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self.submodules.crg = _CRG(platform)
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sdram_geom = sdram.GeomSettings(
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bank_a=3,
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row_a=16,
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col_a=10
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)
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sdram_timing = sdram.TimingSettings(
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tRP=self.ns(15),
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tRCD=self.ns(15),
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tWR=self.ns(15),
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tWTR=2,
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tREFI=self.ns(7800, False),
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tRFC=self.ns(70),
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req_queue_size=8,
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read_time=32,
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write_time=16
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)
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self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
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self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing)
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# BIOS is in SPI flash
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spiflash_pads = platform.request("spiflash")
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spiflash_pads.clk = Signal()
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self.specials += Instance("STARTUPE2",
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i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
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i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
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self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
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self.flash_boot_address = 0xb00000
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self.register_rom(self.spiflash.bus)
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class MiniSoC(BaseSoC):
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csr_map = {
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"ethphy": 12,
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"ethmac": 13,
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}
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csr_map.update(BaseSoC.csr_map)
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interrupt_map = {
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"ethmac": 2,
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}
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interrupt_map.update(BaseSoC.interrupt_map)
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def __init__(self, platform, **kwargs):
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BaseSoC.__init__(self, platform, **kwargs)
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self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
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self.add_wb_slave(lambda a: a[26:29] == 3, self.ethmac.bus)
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self.add_cpu_memory_region("ethmac_mem", 0xb0000000, 0x2000)
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default_subtarget = BaseSoC
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