115 lines
2.6 KiB
Python
115 lines
2.6 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFOBuffered as SyncFIFO
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.record import *
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from miscope.std import *
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class RunLengthEncoder(Module, AutoCSR):
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def __init__(self, width, length=1024):
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self.width = width
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self.length = length
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self.sink = Record(dat_layout(width))
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self.source = Record(dat_layout(width))
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self._enable = CSRStorage()
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###
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enable = self._enable.storage
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sink_d = Record(dat_layout(width))
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self.sync += If(self.sink.stb, sink_d.eq(self.sink))
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cnt = Signal(max=length)
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cnt_inc = Signal()
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cnt_reset = Signal()
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cnt_max = Signal()
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self.sync += \
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If(cnt_reset,
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cnt.eq(1),
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).Elif(cnt_inc,
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cnt.eq(cnt+1)
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)
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self.comb += cnt_max.eq(cnt == length)
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change = Signal()
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self.comb += change.eq(self.sink.stb & (self.sink.dat != sink_d.dat))
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fsm = FSM(reset_state="BYPASS")
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self.submodules += fsm
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fsm.act("BYPASS",
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sink_d.connect(self.source),
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cnt_reset.eq(1),
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If(enable & ~change & self.sink.stb, NextState("COUNT"))
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)
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fsm.act("COUNT",
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cnt_inc.eq(self.sink.stb),
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If(change | cnt_max | ~enable,
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self.source.stb.eq(1),
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self.source.dat[width-1].eq(1), # Set RLE bit
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self.source.dat[:flen(cnt)].eq(cnt),
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NextState("BYPASS")
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)
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),
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class Recorder(Module, AutoCSR):
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def __init__(self, width, depth):
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self.width = width
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self.trig_sink = Record(hit_layout())
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self.dat_sink = Record(dat_layout(width))
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self._trigger = CSR()
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self._length = CSRStorage(bits_for(depth))
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self._offset = CSRStorage(bits_for(depth))
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self._done = CSRStatus()
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self._read_en = CSR()
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self._read_empty = CSRStatus()
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self._read_dat = CSRStatus(width)
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###
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fifo = InsertReset(SyncFIFO(width, depth))
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self.submodules += fifo
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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self.comb += [
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self._read_empty.status.eq(~fifo.readable),
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self._read_dat.status.eq(fifo.dout),
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]
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fsm.act("IDLE",
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If(self._trigger.re & self._trigger.r,
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NextState("PRE_HIT_RECORDING"),
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fifo.reset.eq(1),
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),
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fifo.re.eq(self._read_en.re & self._read_en.r),
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self._done.status.eq(1)
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)
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fsm.act("PRE_HIT_RECORDING",
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fifo.we.eq(self.dat_sink.stb),
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fifo.din.eq(self.dat_sink.dat),
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fifo.re.eq(fifo.level >= self._offset.storage),
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If(self.trig_sink.stb & self.trig_sink.hit, NextState("POST_HIT_RECORDING"))
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)
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fsm.act("POST_HIT_RECORDING",
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fifo.we.eq(self.dat_sink.stb),
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fifo.din.eq(self.dat_sink.dat),
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If(~fifo.writable | (fifo.level >= self._length.storage), NextState("IDLE"))
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)
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