224 lines
10 KiB
Plaintext
224 lines
10 KiB
Plaintext
[> 2021.XX, planned for August 2021
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-----------------------------------
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[> Issues resolved
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------------------
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- wishbone/UpConverter: Fix SEL propagation.
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[> Added Features
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-----------------
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- cpu/vexriscv: Add CFU support.
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- soc/controller: Add separate SoC/CPU reset fields.
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[> API changes/Deprecation
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--------------------------
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- soc_core: --integrated-rom-file argument renamed to --integrated-rom-init.
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[> 2021.04, released on May 3th 2021
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------------------------------------
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[> Issues resolved
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------------------
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- litex_term: Fix Windows/OS-X support.
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- soc/USB-ACM: Fix reset clock domain.
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- litex_json2dts: Various fixes/improvements.
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- cores/clock: Fix US(P)IDELAYCTRL reset sequence.
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- cpu/Vexriscv: Fix Lite variant ABI (has multiplier so can use rv32im).
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- BIOS: Fix various compiler warnings.
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- LiteSDCard: Fix various issues, enable multiblock reads/writes and improve performance.
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- CSR: Fix address wrapping within a CSRBank.
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- soc/add_etherbone: Fix UDPIPCore clock domain.
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- stream/Gearbox: Fix some un-supported cases.
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- cpu/VexRiscv-SMP: Fix build on Intel/Altera devices with specific RAM implementation.
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- timer: Fix AutoDoc.
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- Microwatt/Ethernet: Fix build.
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- soc/software: Link with compiler instead of ld.
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[> Added Features
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-----------------
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- Lattice-NX: Allow up to 320KB RAMs.
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- BIOS: Allow compilation with UART disabled.
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- litex_json2dts: Simplify/Improve and allow VexRiscv/Mor1kx support.
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- BIOS/i2c: Improve cmd_i2c.
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- BIOS/liblitedram: Various improvements for DDR4/LPDDR.
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- cores/Timer: Add initial unit test.
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- cores: Add initial JTAGBone support on Xilinx FPGAs.
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- litex_term: Improve JTAG-UART support.
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- litex_server: Add JTAGBone support.
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- VexRiscv-SMP: Add --without-out-of-order and --with-wishbone-memory capabilities.
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- BIOS: Allow specify TRIPLE with LITEX_ENV_CC_TRIPLE.
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- litex_client: Add simple --read/--write support.
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- OpenFPGALoader: Add flash method.
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- litex_sim: Add GTKWave savefile generator.
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- litex_term: Add nios2-terminal support.
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- cpu/mor1kx: Add initial SMP support.
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- interconnect/axi: Add tkeep support.
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- cores/gpio: Add IRQ support to GPIOIn.
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- cpu: Add initial lowRISC's Ibex support.
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- build/xilinx/Vivado: Allow tcl script to be added as ip.
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- cores/uart: Rewrite PHYs to reduce resource usage and improve readability.
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- cores/pwm: Add configurable default enable/width/period values.
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- cores/leds: Add optional dimming (through PWM).
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- soc/add_pcie: Allow disabling MSI when not required.
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- export/svd: Add constants to SVD export.
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- BIOS: Allow dynamic Ethernet IP address.
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- BIOS: Add boot command to boot from memory.
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- cores: Add simple VideoOut core with Terminal, ColorBards, Framebuffer + various PHYs (VGA, DVI, HDMI, etc...).
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- csr/EventSourceProcess: Add rising edge support and edge selection.
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- soc/integration: Cleanup/Simplify soc_core/builder.
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- soc/integrated_rom: Add automatic BIOS ROM resize to minimize blockram usage and improve flexibility.
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- interconnect/axi: Add AXILite Clock Domain Crossing.
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- cores/xadc: Add Ultrascale support.
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- soc/add_ethernet: Allow nrxslots/ntxslots configuration.
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- cpu/VexRiscv-SMP: Integrate FPU/RVC support.
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- soc/add_csr: Add auto-allocation mode and switch to it in LiteX's code base.
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- soc/BIOS: Add method to check BIOS requirements during the build and improve error message when not satisfied.
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- LiteEth: Add initial timestamping support.
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- litex_client: Add optional filter to --regs.
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- LiteDRAM: Add LPDDR4 support.
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- BIOS/netboot: Allow specifying .json file.
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- cores/clock: Add initial Gowin GW1N PLL support.
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- LiteSDCard: Add IRQ support.
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[> API changes/Deprecation
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--------------------------
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- platforms/targets: Move all platforms/targets to https://github.com/litex-hub/litex-boards.
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- litex_term: Remove flashing capability.
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- cores/uart: Disable dynamic baudrate by default (Unused and save resources).
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[> 2020.12, released on December 30th 2020
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------------------------------------------
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[> Issues resolved
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------------------
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- fix SDCard writes.
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- fix crt0 .data initialize on SERV/Minerva.
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- fix Zynq7000 AXI HP Slave integration.
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[> Added Features
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------------------
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- Wishbone2CSR: Add registered version and use it on system with SDRAM.
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- litex_json2dts: Add Mor1kx DTS generation support.
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- Build: Add initial Radiant support for NX FPGA family.
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- SoC: Allow ROM to be optionally writable (for contents overwrite over UARTBone/Etherbone).
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- LiteSDCard: Improve BIOS support.
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- UARTBone: Add clock domain support.
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- Clocking: Uniformize reset on iCE40PLL/ECP5PLL.
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- LiteDRAM: Improve calibration and add BIOS debug commands.
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- Clocking: Add initial Ultrascale+ support.
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- Sim: Allow dynamic enable/disable of tracing.
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- BIOS: Improve memtest and report.
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- BIOS: Rename/reorganize commands.
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- litex_server: Simplify usage with PCIe and add debug parameter.
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- LitePCIe: Add Ultrascale(+) support up to Gen3 X16.
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- LiteSATA: Add BIOS/Boot integration.
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- Add litex_cli to provides common RemoteClient functions: get identifier, dump regs, etc...
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- LiteDRAM: Simplify BIST integration.
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- Toolchains/Programmers: Improve checks/error reporting.
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- BIOS: add leds command.
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- SoC: Do a full reset of the SoC on reboot (not only the CPU).
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- Etherbone: Improve efficiency/performance.
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- LiteDRAM: Improve DDR4/DDR3 calibration.
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- Build: Add initial Oxide support for NX FPGA family.
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- Clock/RAM: Reorganize for better modularity.
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- SPI-OPI: Various improvements for Betrusted.
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- litex_json2dts: Improvements to use it with mor1kx and VexRiscv-SMP.
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- Microwatt: Add IRQ support.
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- BIOS: Add i2c_scan command.
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- Builder: Simplify Documentation generation with --doc args on targets.
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- CSR: Add documentation to EventManager registers.
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- BIOS: Allow disabling timestamp for reproducible builds.
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- Symbiflow: Remove workarounds on targets.
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- litex_server: Simplify use on PCIe, allow direct CommXY use in scripts to bypass litex_server.
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- Zynq7000: Improve PS7 configuration support (now supporting .xci/preset/dict)
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- CV32E40P: Improve OBI efficiency.
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- litex_term: Improve upload speed with CRC check enabled, deprecate --no-crc (no longer useful).
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- BIOS: Add mem_list command to list available memory and use mem_xy commands on them.
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- litex_term: Add Crossover and JTAG_UART support.
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- Software: Add minimal bare metal demo app.
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- UART: Add Crossover+Bridge support.
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- VexRiscv-SMP: Integrate AES support.
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- LitePCIe: Allow AXI mastering from FPGA (AXI-Lite and Full).
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- mor1kx: Add standard+fpu and linux+fpu variants.
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[> API changes/Deprecation
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--------------------------
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- BIOS: commands have been renamed/reorganized.
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- LiteDRAM: rdcmdphase/wrcmdphase no longer exposed.
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- CSR: change default csr_data_width from 8 to 32.
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[> 2020.08, released on August 7th 2020
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---------------------------------------
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[> Issues resolved
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------------------
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- Fix flush_cpu_icache on VexRiscv.
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- Fix `.data` section placed in rom (#566)
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[> Added Features
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------------------
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- Properly integrate Minerva CPU.
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- Add nMigen dependency.
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- Pluggable CPUs.
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- BIOS history, autocomplete.
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- Improve boards's programmers.
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- Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
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- Speedup Memtest using an LFSR.
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- Add LedChaser on boards.
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- Improve WishboneBridge.
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- Improve Diamond constraints.
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- Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
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- Add CV32E40P CPU support (ex RI5CY).
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- JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
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- Add Symbiflow experimental support on Arty.
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- Add SDCard (SPI and SD modes) boot from FAT/exFAT filesystems with FatFs.
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- Simplify boot with boot.json configuration file.
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- Revert to a single crt0 (avoid ctr/xip variants).
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- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
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- Add AXI-Lite bus standard support.
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- Add VexRiscv SMP CPU support.
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[> API changes/Deprecation
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--------------------------
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- Add --build --load arguments to targets.
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- Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
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- Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
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- Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
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- Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
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- Rename --gateware-toolchain target parameter to --toolchain.
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- Integrate Zynq's PS7 as a regular CPU (zynq7000) and deprecate SoCZynq.
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[> 2020.04, released on April 28th, 2020
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----------------------------------------
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[> Description
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--------------
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First release of LiteX and the ecosystem of cores!
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LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
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Cores/SoCs (with or without CPU).
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The common components of a SoC are provided directly:
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- Buses and Streams (Wishbone, AXI, Avalon-ST)
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- Interconnect
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- Common cores (RAM, ROM, Timer, UART, etc...)
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- CPU wrappers/integration
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- etc...
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And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
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PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
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It also provides build backends for open-source and vendors toolchains.
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[> Issues resolved
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------------------
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- NA
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[> Added Features
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------------------
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- NA
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[> API changes/Deprecation
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--------------------------
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- https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.
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