34 lines
884 B
Python
34 lines
884 B
Python
import os
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import pty
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import time
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from migen.fhdl.std import *
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from migen.flow.actor import Sink, Source
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class UARTPHYSim(Module):
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def __init__(self, pads, *args, **kwargs):
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self.sink = Sink([("data", 8)])
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self.source = Source([("data", 8)])
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self.comb += [
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pads.source_stb.eq(self.sink.stb),
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pads.source_data.eq(self.sink.data),
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self.sink.ack.eq(pads.source_ack),
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self.source.stb.eq(pads.sink_stb),
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self.source.data.eq(pads.sink_data),
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pads.sink_ack.eq(self.source.ack)
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]
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m, s = pty.openpty()
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name = os.ttyname(s)
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print("UART tty: "+name)
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time.sleep(0.5) # pause for user
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f = open("/tmp/simserial", "w")
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f.write(os.ttyname(s))
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f.close()
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def do_exit(self, *args, **kwargs):
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os.remove("/tmp/simserial")
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