53 lines
1.7 KiB
Python
53 lines
1.7 KiB
Python
# Simple Processor Interface
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from migen.fhdl.structure import *
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from migen.bank.description import *
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from migen.flow.actor import *
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class Collector(Actor):
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def __init__(self, layout, depth=1024):
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super().__init__(("sink", Sink, layout))
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self._depth = depth
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self._dw = sum(len(s) for s in self.token("sink").flatten())
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# TODO: reg_wc should have atomic update
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self._reg_wa = RegisterField("write_address", bits_for(self._depth-1), access_bus=READ_WRITE, access_dev=READ_WRITE)
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self._reg_wc = RegisterField("write_count", bits_for(self._depth), access_bus=READ_WRITE, access_dev=READ_WRITE)
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self._reg_ra = RegisterField("read_address", bits_for(self._depth-1), access_bus=READ_WRITE, access_dev=READ_ONLY)
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self._reg_rd = RegisterField("read_data", self._dw, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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def get_registers(self):
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return [self._reg_wa, self._reg_wc, self._reg_ra, self._reg_rd]
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def get_fragment(self):
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wa = Signal(BV(bits_for(self._depth-1)))
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dummy = Signal(BV(self._dw))
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wd = Signal(BV(self._dw))
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we = Signal()
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wp = MemoryPort(wa, dummy, wd, we)
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ra = Signal(BV(bits_for(self._depth-1)))
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rd = Signal(BV(self._dw))
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rp = MemoryPort(ra, rd)
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mem = Memory(self._dw, self._depth, wp, rp)
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comb = [
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If(self._reg_wc.field.r != 0,
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self.endpoints["sink"].ack.eq(1),
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If(self.endpoints["sink"].stb,
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self._reg_wa.field.we.eq(1),
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self._reg_wc.field.we.eq(1),
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we.eq(1)
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)
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),
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self._reg_wa.field.w.eq(self._reg_wa.field.r + 1),
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self._reg_wc.field.w.eq(self._reg_wc.field.r - 1),
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wa.eq(self._reg_wa.field.r),
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wd.eq(Cat(*self.token("sink").flatten())),
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ra.eq(self._reg_ra.field.r),
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self._reg_rd.field.w.eq(rd)
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]
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return Fragment(comb, memories=[mem])
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