47 lines
1.4 KiB
Python
47 lines
1.4 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.bank.description import *
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from milkymist.dvisampler.edid import EDID
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from milkymist.dvisampler.clocking import Clocking
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from milkymist.dvisampler.datacapture import DataCapture
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from milkymist.dvisampler.charsync import CharSync
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from milkymist.dvisampler.chansync import ChanSync
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class DVISampler(Module, AutoReg):
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def __init__(self, inversions=""):
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self.submodules.edid = EDID()
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self.sda = self.edid.sda
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self.scl = self.edid.scl
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self.submodules.clocking = Clocking()
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self.clk = self.clocking.clkin
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for datan in "012":
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name = "data" + str(datan)
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invert = datan in inversions
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signame = name + "_n" if invert else name
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s = Signal(name=signame)
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setattr(self, signame, s)
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cap = DataCapture(8, invert)
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setattr(self.submodules, name + "_cap", cap)
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self.comb += [
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cap.pad.eq(s),
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cap.serdesstrobe.eq(self.clocking.serdesstrobe)
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]
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charsync = CharSync()
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setattr(self.submodules, name + "_charsync", charsync)
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self.comb += charsync.raw_data.eq(cap.d)
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self.submodules.chansync = ChanSync()
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self.comb += [
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self.chansync.char_synced.eq(self.data0_charsync.synced & \
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self.data1_charsync.synced & self.data2_charsync.synced),
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self.chansync.data_in0.eq(self.data0_charsync.data),
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self.chansync.data_in1.eq(self.data1_charsync.data),
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self.chansync.data_in2.eq(self.data2_charsync.data),
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]
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