Sebastien Bourdeauducq 0493212124 bus: simplify and cleanup ... Unify slave and master interfaces Remove signal direction suffixes Generic simple interconnect Wishbone point-to-point interconnect Description filter (get_name) Misc cleanups		2012-02-15 16:30:16 +01:00
..
actorlib	Use enumerate(x) instead of zip(range(x), x)	2012-02-02 21:28:00 +01:00
bank	Use double quotes for all strings	2012-02-14 13:12:43 +01:00
bus	bus: simplify and cleanup	2012-02-15 16:30:16 +01:00
corelogic	Use double quotes for all strings	2012-02-14 13:12:43 +01:00
fhdl	fhdl: do not attempt slicing non-array signals to keep Verilog happy	2012-02-06 18:07:02 +01:00
flow	Use double quotes for all strings	2012-02-14 13:12:43 +01:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00