179 lines
10 KiB
ReStructuredText
179 lines
10 KiB
ReStructuredText
.. _simulating:
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Simulating a Migen design
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#########################
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Migen allows you to easily simulate your FHDL design and interface it with arbitrary Python code.
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To interpret the design, the FHDL structure is simply converted into Verilog and then simulated using an external program (e.g. Icarus Verilog). This is is intrinsically compatible with VHDL/Verilog instantiations from Migen and maximizes software reuse.
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To interface the external simulator to Python, a VPI task is called at each clock cycle and implement the test bench functionality proper - which can be fully written in Python.
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Signals inside the simulator can be read and written using VPI as well. This is how the Python test bench generates stimulus and obtains the values of signals for processing.
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.. _vpisetup:
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Installing the VPI module
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*************************
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To communicate with the external simulator, Migen uses a UNIX domain socket and a custom protocol which is handled by a VPI plug-in (written in C) on the simulator side.
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To build and install this plug-in, run the following commands from the ``vpi`` directory: ::
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make [INCDIRS=-I/usr/...]
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make install [INSTDIR=/usr/...]
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The variable ``INCDIRS`` (default: empty) can be used to give a list of paths where to search for the include files. This is useful considering that different Linux distributions put the ``vpi_user.h`` file in various locations.
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The variable ``INSTDIR`` (default: ``/usr/lib/ivl``) specifies where the ``migensim.vpi`` file is to be installed.
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This plug-in is designed for Icarus Verilog, but can probably be used with most Verilog simulators with minor modifications.
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The generic simulator object
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****************************
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The generic simulator object (``migen.sim.generic.Simulator``) is the central component of the simulation.
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Creating a simulator object
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===========================
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The constructor of the ``Simulator`` object takes the following parameters:
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#. The module to simulate.
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#. A top-level object (see :ref:`toplevel`). With the default value of ``None``, the simulator creates a default top-level object itself.
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#. A simulator runner object (see :ref:`simrunner`). With the default value of ``None``, Icarus Verilog is used with the default parameters.
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#. The name of the UNIX domain socket used to communicate with the external simulator through the VPI plug-in (default: "simsocket").
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#. Additional keyword arguments (if any) are passed to the Verilog conversion function.
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For proper initialization and clean-up, the simulator object should be used as a context manager, e.g. ::
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with Simulator(tb) as s:
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s.run()
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Running the simulation
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======================
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Running the simulation is achieved by calling the ``run`` method of the ``Simulator`` object.
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It takes an optional parameter ``ncycles`` that defines the maximum number of clock cycles that this call simulates. The default value of ``None`` sets no cycle limit.
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The cycle counter
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=================
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Simulation functions can read the current simulator cycle by reading the ``cycle_counter`` property of the ``Simulator``. The cycle counter's value is 0 for the cycle immediately following the reset cycle.
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Simplified simulation set-up
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============================
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Most simulations are run in the same way and do not need the slightly heavy syntax needed to create and run a Simulator object. There is a function that exposes the most common features with a simpler syntax: ::
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run_simulation(module, ncycles=None, vcd_name=None, keep_files=False)
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Module-level simulation API
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***************************
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Simulation functions and generators
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===================================
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Whenever a ``Module`` declares a ``do_simulation`` method, it is executed at each cycle and can manipulate values from signal and memories (as explained in the next section).
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Instead of defining such a method, ``Modules`` can declare a ``gen_simulation`` generator that is initialized at the beginning of the simulation, and yields (usually multiple times) to proceed to the next simulation cycle.
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Simulation generators can yield an integer in order to wait for that number of cycles, or yield nothing (``None``) to wait for 1 cycle.
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Reading and writing values
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===========================
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Simulation functions and generators take as parameter a special object that gives access to the values of the signals of the current module using the regular Python read/write syntax. Nested objects, lists and dictionaries containing signals are supported, as well as Migen memories, for reading and writing.
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Here are some examples: ::
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def do_simulation(self, selfp):
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selfp.foo = 42
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self.last_foo_value = selfp.foo
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selfp.dut.banks[2].bar["foo"] = 1
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self.last_memory_data = selfp.dut.mem[self.memory_index]
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The semantics of reads and writes (respectively immediately before and after the clock edge) match those of the non-blocking assignment in Verilog. Note that because of Verilog's design, reading "variable" signals (i.e. written to using blocking assignment) directly may give unexpected and non-deterministic results and is not supported. You should instead read the values of variables after they have gone through a non-blocking assignment in the same ``always`` block.
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Those constructs are syntactic sugar for calling the ``Simulator`` object's methods ``rd`` and ``wr``, that respectively read and write data from and to the simulated design. The simulator object can be accessed as ``selfp.simulator``, and for special cases it is sometimes desirable to call the lower-level methods directly.
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The ``rd`` method takes the FHDL ``Signal`` object to read and returns its value as a Python integer. The returned integer is the value of the signal immediately before the clock edge.
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The ``wr`` method takes a ``Signal`` object and the value to write as a Python integer. The signal takes the new value immediately after the clock edge.
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References to FHDL ``Memory`` objects can also be passed to the ``rd`` and ``wr`` methods. In this case, they take an additional parameter for the memory address.
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Simulation termination management
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=================================
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Simulation functions and generators can raise the ``StopSimulation`` exception. It is automatically raised when a simulation generator is exhausted. This exception disables the current simulation function, i.e. it is no longer run by the simulator. The simulation is over when all simulation functions are disabled (or the specified maximum number of cycles, if any, has been reached - whichever comes first).
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Some simulation modules only respond to external stimuli - e.g. the ``bus.wishbone.Tap`` that snoops on bus transactions and prints them on the console - and have simulation functions that never end. To deal with those, the new API introduces "passive" simulation functions that are not taken into account when deciding to continue to run the simulation. A simulation function is declared passive by setting a "passive" attribute on it that evaluates to True. Raising ``StopSimulation`` in such a function still makes the simulator stop running it for the rest of the simulation.
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When starting the simulation of a design that contains no simulation functions or only passive simulation functions, the simulation will continue until the specified number of cycles is reached. The ``ncycles`` parameter is mandatory in this case.
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.. _simrunner:
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The external simulator runner
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*****************************
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Role
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====
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The runner object is responsible for starting the external simulator, loading the VPI module, and feeding the generated Verilog into the simulator.
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It must implement a ``start`` method, called by the ``Simulator``, which takes two strings as parameters. They contain respectively the Verilog source of the top-level design and the converted module.
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Icarus Verilog support
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======================
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Migen comes with a ``migen.sim.icarus.Runner`` object that supports Icarus Verilog.
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Its constructor has the following optional parameters:
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#. ``extra_files`` (default: ``None``): lists additional Verilog files to simulate.
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#. ``top_file`` (default: "migensim_top.v"): name of the temporary file containing the top-level.
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#. ``dut_file`` (default: "migensim_dut.v"): name of the temporary file containing the converted fragment.
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#. ``vvp_file`` (default: ``None``): name of the temporary file compiled by Icarus Verilog. When ``None``, becomes ``dut_file + "vp"``.
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#. ``keep_files`` (default: ``False``): do not delete temporary files. Useful for debugging.
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.. _toplevel:
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The top-level object
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********************
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Role of the top-level object
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============================
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The top-level object is responsible for generating the Verilog source for the top-level test bench.
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It must implement a method ``get`` that takes as parameter the name of the UNIX socket the VPI plugin should connect to, and returns the full Verilog source as a string.
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It must have the following attributes (which are read by the ``Simulator`` object):
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* ``clk_name``: name of the clock signal.
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* ``rst_name``: name of the reset signal.
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* ``dut_type``: module type of the converted fragment.
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* ``dut_name``: name used for instantiating the converted fragment.
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* ``top_name``: name/module type of the top-level design.
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Role of the generated Verilog
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=============================
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The generated Verilog must:
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#. instantiate the converted fragment and connect its clock and reset ports.
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#. produce a running clock signal.
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#. assert the reset signal for the first cycle and deassert it immediately after.
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#. at the beginning, call the task ``$migensim_connect`` with the UNIX socket name as parameter.
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#. at each rising clock edge, call the task ``$migensim_tick``. It is an error to call ``$migensim_tick`` before a call to ``$migensim_connect``.
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#. set up the optional VCD output file.
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The generic top-level object
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============================
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Migen comes with a ``migen.sim.generic.TopLevel`` object that implements the above behaviour. It should be usable in the majority of cases.
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The main parameters of its constructor are the output VCD file (default: ``None``) and the levels of hierarchy that must be present in the VCD (default: 1).
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