62 lines
2.1 KiB
Python
62 lines
2.1 KiB
Python
from mibuild.generic_platform import *
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from mibuild.xilinx import XilinxPlatform
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from mibuild.xilinx.programmer import XC3SProg
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_io = [
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("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
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("clk32", 0, Pins("P94"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("P105"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")),
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Subsignal("rx", Pins("P101"), IOStandard("LVCMOS33"), Misc("PULLUP"))
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("P38")),
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Subsignal("clk", Pins("P70")),
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Subsignal("mosi", Pins("P64")),
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Subsignal("miso", Pins("P65"), Misc("PULLUP")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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("spiflash2x", 0,
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Subsignal("cs_n", Pins("P38")),
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Subsignal("clk", Pins("P70")),
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Subsignal("dq", Pins("P64", "P65")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
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("sdram", 0,
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Subsignal("a", Pins("P140 P139 P138 P137 P46 P45 P44",
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"P43 P41 P40 P141 P35 P34")),
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Subsignal("ba", Pins("P143 P142")),
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Subsignal("cs_n", Pins("P1")),
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Subsignal("cke", Pins("P33")),
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Subsignal("ras_n", Pins("P2")),
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Subsignal("cas_n", Pins("P5")),
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Subsignal("we_n", Pins("P6")),
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Subsignal("dq", Pins("P9 P10 P11 P12 P14 P15 P16 P8 P21 P22 P23 P24 P26 P27 P29 P30")),
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Subsignal("dm", Pins("P7 P17")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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)
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]
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_connectors = [
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("A", "P48 P51 P56 P58 P61 P66 P67 P75 P79 P81 P83 P85 P88 P93 P98 P100"),
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("B", "P99 P97 P92 P87 P84 P82 P80 P78 P74 P95 P62 P59 P57 P55 P50 P47"),
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("C", "P114 P115 P116 P117 P118 P119 P120 P121 P123 P124 P126 P127 P131 P132 P133 P134")
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]
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class Platform(XilinxPlatform):
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identifier = 0x5050
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default_clk_name = "clk32"
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default_clk_period = 31.25
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def __init__(self):
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XilinxPlatform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors)
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def create_programmer(self):
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return XC3SProg("papilio", "bscan_spi_lx9_papilio.bit")
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