Jiaxun Yang 1e21105731 test/test_integration: Add test for various bus options ... Test bus standard/data-width/address-width/interconnect combinations. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>		2024-12-20 12:22:39 +00:00
..
__init__.py
test_avalon_mm.py
test_axi.py	soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.	2023-10-27 10:55:13 +02:00
test_axi_lite.py
test_axi_stream.py	test: Add minimal test_axi_stream test (Just syntax check for now).	2022-09-08 11:53:05 +02:00
test_bitbang.py
test_clock.py
test_code_8b10b.py
test_csr.py
test_ecc.py
test_emif.py
test_fifosyncmacro.py	test: FifoSyncMacro: Use F4PGA instead of deprecated Symbiflow	2022-06-17 16:27:25 +02:00
test_gearbox.py
test_hyperbus.py	soc/cores/hyperbus: Add automatic read burst detection.	2024-08-30 11:53:14 +02:00
test_i2c.py	test_i2c: whitespace cleanups	2024-07-20 15:45:44 +10:00
test_i2s.py
test_icap.py	cores/icap/ICAP: Add Register read capability.	2021-10-04 17:22:57 +02:00
test_integration.py
test_led.py
test_packet.py
test_prbs.py
test_reduce.py
test_spi.py	test: add SPDX License identifier to header and specify file is part of LiteX.	2020-08-23 15:40:21 +02:00
test_spi_mmap.py
test_spi_opi.py
test_stream.py	stream/Buffer: Integrate PipeValid/PipeReady (both configurable) and add tests.	2022-09-07 08:59:37 +02:00
test_timer.py
test_wishbone.py