47 lines
1.1 KiB
Python
47 lines
1.1 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog
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class LM32:
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def __init__(self):
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self.inst = Instance("lm32_top",
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[("I_ADR_O", BV(32)),
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("I_DAT_O", BV(32)),
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("I_SEL_O", BV(4)),
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("I_CYC_O", BV(1)),
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("I_STB_O", BV(1)),
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("I_WE_O", BV(1)),
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("I_CTI_O", BV(3)),
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("I_LOCK_O", BV(1)),
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("I_BTE_O", BV(1)),
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("D_ADR_O", BV(32)),
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("D_DAT_O", BV(32)),
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("D_SEL_O", BV(4)),
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("D_CYC_O", BV(1)),
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("D_STB_O", BV(1)),
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("D_WE_O", BV(1)),
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("D_CTI_O", BV(3)),
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("D_LOCK_O", BV(1)),
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("D_BTE_O", BV(1))],
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[("interrupt", BV(32)),
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("ext_break", BV(1)),
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("I_DAT_I", BV(32)),
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("I_ACK_I", BV(1)),
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("I_ERR_I", BV(1)),
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("I_RTY_I", BV(1)),
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("D_DAT_I", BV(32)),
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("D_ACK_I", BV(1)),
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("D_ERR_I", BV(1)),
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("D_RTY_I", BV(1))],
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clkport="clk_i",
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rstport="rst_i",
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name="lm32")
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def get_fragment(self):
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return Fragment(instances=[self.inst])
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cpus = [LM32() for i in range(4)]
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frag = Fragment()
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for cpu in cpus:
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frag += cpu.get_fragment()
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print(verilog.convert(frag, set([cpus[0].inst.ins["interrupt"], cpus[0].inst.outs["I_WE_O"]])))
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