298 lines
11 KiB
Python
298 lines
11 KiB
Python
#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022-2023 MoTeC
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# Copyright (c) 2022-2023 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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import inspect
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from migen import Record
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from litex.gen.sim import run_simulation
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from litex.soc.cores.spi.spi_mmap import (
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SPIMaster,
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SPIMMAP,
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SPI_SLOT_BITORDER_LSB_FIRST,
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SPI_SLOT_BITORDER_MSB_FIRST,
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SPI_SLOT_LENGTH_16B,
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SPI_SLOT_LENGTH_24B,
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SPI_SLOT_LENGTH_32B,
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SPI_SLOT_LENGTH_8B,
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SPI_SLOT_MODE_0,
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SPI_SLOT_MODE_3,
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)
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verbose = None
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def unittest_verbosity():
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"""Return the verbosity setting of the currently running unittest
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program, or 0 if none is running.
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"""
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frame = inspect.currentframe()
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while frame:
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self = frame.f_locals.get("self")
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if isinstance(self, unittest.TestProgram):
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return self.verbosity
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frame = frame.f_back
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return 0
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def vprint(*args):
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global verbose
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if verbose is None:
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verbose = unittest_verbosity()
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if verbose > 1:
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print(*args)
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class TestSPIMMAP(unittest.TestCase):
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def test_spi_master(self):
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pads = Record([("clk", 1), ("cs_n", 4), ("mosi", 1), ("miso", 1)])
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dut = SPIMaster(pads=pads, data_width=32, sys_clk_freq=int(100e6))
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def generator(dut):
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data = [
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0x12345678,
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0xDEADBEEF,
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]
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# data = [
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# 0x80000001,
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# 0x80000001,
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# ]
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# Config: Mode0, Loopback, Sys-Clk/4
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yield dut.loopback.eq(1)
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yield dut.clk_divider.eq(4)
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yield dut.mode.eq(SPI_SLOT_MODE_0)
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yield
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yield dut.mosi.eq(data[0])
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yield dut.cs.eq(0b0001)
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yield dut.length.eq(32)
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yield dut.start.eq(1)
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yield
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yield dut.start.eq(0)
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while (yield dut.done) == 0b0:
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yield
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yield dut.cs.eq(0b0000)
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for i in range(16):
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yield
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print(f"mosi_data : {(yield dut.miso):08x}")
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# Config: Mode3, Loopback, Sys-Clk/4.
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yield dut.loopback.eq(1)
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yield dut.clk_divider.eq(4)
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yield dut.mode.eq(SPI_SLOT_MODE_3)
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yield
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yield dut.mosi.eq(data[0])
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yield dut.cs.eq(0b0001)
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yield dut.length.eq(32)
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yield dut.start.eq(1)
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yield
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yield dut.start.eq(0)
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while (yield dut.done) == 0b0:
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yield
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yield dut.cs.eq(0b0000)
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for i in range(16):
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yield
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print(f"mosi_data : {(yield dut.miso):08x}")
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# Config: Mode0, Loopback, Sys-Clk/8.
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yield dut.loopback.eq(1)
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yield dut.clk_divider.eq(8)
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yield dut.mode.eq(SPI_SLOT_MODE_0)
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yield
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yield dut.mosi.eq(data[1])
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yield dut.cs.eq(0b0001)
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yield dut.length.eq(32)
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yield dut.start.eq(1)
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yield
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yield dut.start.eq(0)
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while (yield dut.done) == 0b0:
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yield
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yield dut.cs.eq(0b0000)
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for i in range(16):
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yield
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print(f"mosi_data : {(yield dut.miso):08x}")
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# Config: Mode3, Loopback, Sys-Clk/8.
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yield dut.loopback.eq(1)
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yield dut.clk_divider.eq(8)
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yield dut.mode.eq(SPI_SLOT_MODE_3)
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yield
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yield dut.mosi.eq(data[1])
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yield dut.cs.eq(0b0001)
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yield dut.length.eq(32)
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yield dut.start.eq(1)
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yield
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yield dut.start.eq(0)
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while (yield dut.done) == 0b0:
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yield
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yield dut.cs.eq(0b0000)
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for i in range(16):
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yield
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print(f"mosi_data : {(yield dut.miso):08x}")
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run_simulation(dut, generator(dut), vcd_name="sim.vcd")
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def mmap_test(self, length, bitorder, data, vcd_name=None, sel_override=None, wait=0):
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pads = Record([("clk", 1), ("cs_n", 4), ("mosi", 1), ("miso", 1)])
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dut = SPIMMAP(
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pads=pads,
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data_width=32,
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sys_clk_freq=int(100e6), # only used for clock settle time!
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tx_fifo_depth=32,
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rx_fifo_depth=32,
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)
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def generator(dut):
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# Minimal setup - spi_mmap ctrl defaults are everything enabled and:
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# SPI_SLOT_MODE_3, SPI_SLOT_LENGTH_32B, SPI_SLOT_BITORDER_MSB_FIRST, loopback, divider=2, wait=0
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version = yield dut.ctrl._version.status
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vprint(f"version: {version}")
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vprint(f"slot_count: {(yield dut.ctrl.slot_count.status)}")
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# yield dut.ctrl.slot_control0.fields.enable.eq(1)
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# yield dut.ctrl.slot_control0.fields.mode.eq(SPI_SLOT_MODE_3)
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yield dut.ctrl.slot_control0.fields.length.eq(length)
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yield dut.ctrl.slot_control0.fields.bitorder.eq(bitorder)
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# yield dut.ctrl.slot_control0.fields.loopback.eq(1)
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# yield dut.ctrl.slot_control0.fields.divider.eq(2)
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# yield dut.ctrl.slot_control0.fields.enable.eq(1)
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yield dut.ctrl.slot_control0.fields.wait.eq(wait)
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if length == SPI_SLOT_LENGTH_32B:
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spi_length = 32
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sel = 0b1111
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width = 8
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if length == SPI_SLOT_LENGTH_24B:
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spi_length = 24
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sel = 0b1111
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width = 6
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if length == SPI_SLOT_LENGTH_16B:
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spi_length = 16
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sel = 0b0011
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width = 4
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if length == SPI_SLOT_LENGTH_8B:
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spi_length = 8
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sel = 0b0001
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width = 2
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if sel_override:
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sel = sel_override
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vprint(f"spi_length {spi_length} width {width} sel {sel:b} len(data) {len(data)}")
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dut_tx_status = dut.ctrl.tx_status.fields
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dut_rx_status = dut.ctrl.rx_status.fields
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self.assertEqual((yield dut_tx_status.empty), 1)
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self.assertEqual((yield dut_tx_status.full), 0)
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self.assertEqual((yield dut_tx_status.ongoing), 0)
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self.assertEqual((yield dut_tx_status.level), 0)
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self.assertEqual((yield dut_rx_status.empty), 1)
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self.assertEqual((yield dut_rx_status.full), 0)
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self.assertEqual((yield dut_rx_status.ongoing), 0)
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self.assertEqual((yield dut_rx_status.level), 0)
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for d in data:
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vprint(f"write {d:0{width}x}")
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yield from dut.tx_mmap.bus.write(0, d, sel)
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yield
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self.assertEqual((yield dut_tx_status.empty), 0)
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self.assertEqual((yield dut_tx_status.full), 0)
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self.assertEqual((yield dut_tx_status.ongoing), 1)
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self.assertGreater((yield dut_tx_status.level), 0)
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self.assertEqual((yield dut_rx_status.empty), 1)
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self.assertEqual((yield dut_rx_status.full), 0)
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self.assertEqual((yield dut_rx_status.ongoing), 1)
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self.assertEqual((yield dut_rx_status.level), 0)
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tx_empty = -1
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rx_empty = -1
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miso = -1
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mosi = -1
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while (yield dut_rx_status.ongoing) == 0b1 or (yield dut_rx_status.level) != len(data):
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if rx_empty != (rx_empty := (yield dut_rx_status.empty)):
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vprint(f"rx_empty:{rx_empty}")
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if tx_empty != (tx_empty := (yield dut_tx_status.empty)):
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vprint(f"tx_empty:{tx_empty}")
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if mosi != (mosi := (yield dut.tx_rx_engine.spi.mosi)):
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vprint(f"mosi => {mosi:0{width}x}")
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if miso != (miso := (yield dut.tx_rx_engine.spi.miso)):
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vprint(f"miso <= {miso:0{width}x}")
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yield
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yield
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for d in data:
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read = yield from dut.rx_mmap.bus.read(0)
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self.assertEqual(read, d, f"read {read:0{width}x} expect: {d:0{width}x}")
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run_simulation(dut, generator(dut), vcd_name=vcd_name)
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# 32 bit write to 32bit slot
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def test_spi_mmap_32_lsb(self):
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data = [0x12345678, 0x9ABCDEF0]
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self.mmap_test(SPI_SLOT_LENGTH_32B, SPI_SLOT_BITORDER_LSB_FIRST, data, "mmap_32_lsb.vcd")
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def test_spi_mmap_32_msb(self):
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data = [0x12345678, 0x9ABCDEF0]
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self.mmap_test(SPI_SLOT_LENGTH_32B, SPI_SLOT_BITORDER_MSB_FIRST, data, "mmap_32_msb.vcd")
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def test_spi_mmap_24_lsb(self):
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data = [0x123456, 0x789ABC, 0xDEF012]
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self.mmap_test(SPI_SLOT_LENGTH_24B, SPI_SLOT_BITORDER_LSB_FIRST, data, "mmap_24_lsb.vcd")
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def test_spi_mmap_24_msb(self):
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data = [0x123456, 0x789ABC, 0xDEF012]
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self.mmap_test(SPI_SLOT_LENGTH_24B, SPI_SLOT_BITORDER_MSB_FIRST, data, "mmap_24_msb.vcd")
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# 16 bit write to 16bit slot
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def test_spi_mmap_16_lsb(self):
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data = [0x1234, 0x5678, 0x9ABC, 0xDEF0]
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self.mmap_test(SPI_SLOT_LENGTH_16B, SPI_SLOT_BITORDER_LSB_FIRST, data, "mmap_16_lsb.vcd")
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def test_spi_mmap_16_msb(self):
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data = [0x1234, 0x5678, 0x9ABC, 0xDEF0]
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self.mmap_test(SPI_SLOT_LENGTH_16B, SPI_SLOT_BITORDER_MSB_FIRST, data, "mmap_16_msb.vcd")
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# 32 bit write to 16bit slot
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def test_spi_mmap_16_lsb_wb32(self):
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data = [0x1234, 0x5678, 0x9ABC, 0xDEF0]
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self.mmap_test(
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SPI_SLOT_LENGTH_16B,
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SPI_SLOT_BITORDER_LSB_FIRST,
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data,
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"mmap_16_lsb_wb32.vcd",
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sel_override=0b1111,
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)
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def test_spi_mmap_16_msb_wb32(self):
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data = [0x1234, 0x5678, 0x9ABC, 0xDEF0]
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self.mmap_test(
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SPI_SLOT_LENGTH_16B,
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SPI_SLOT_BITORDER_MSB_FIRST,
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data,
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"mmap_16_msb_wb32.vcd",
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sel_override=0b1111,
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)
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# 8 bit write to 8bit slot
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def test_spi_mmap_8_lsb(self):
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data = [0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0]
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self.mmap_test(SPI_SLOT_LENGTH_8B, SPI_SLOT_BITORDER_LSB_FIRST, data, "mmap_8_lsb.vcd")
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def test_spi_mmap_8_msb(self):
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data = [0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0]
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self.mmap_test(SPI_SLOT_LENGTH_8B, SPI_SLOT_BITORDER_MSB_FIRST, data, "mmap_8_msb.vcd")
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def test_spi_mmap_8_msb_wait1(self):
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data = [0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0]
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self.mmap_test(SPI_SLOT_LENGTH_8B, SPI_SLOT_BITORDER_MSB_FIRST, data, "mmap_8_msb_wait1.vcd", wait=1)
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def test_spi_mmap_8_msb_wait8(self):
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data = [0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0]
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self.mmap_test(SPI_SLOT_LENGTH_8B, SPI_SLOT_BITORDER_MSB_FIRST, data, "mmap_8_msb_wait8.vcd", wait=8)
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if __name__ == "__main__":
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unittest.main()
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