38 lines
752 B
Python
38 lines
752 B
Python
from migen.fhdl.std import *
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from migen.bus import asmibus
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from migen.sim.generic import Simulator
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from misoclib.framebuffer import *
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def main():
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hub = asmibus.Hub(16, 128)
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port = hub.get_port()
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hub.finalize()
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dut = Framebuffer(1, port, True)
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fragment = hub.get_fragment() + dut.get_fragment()
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sim = Simulator(fragment)
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sim.run(1)
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def csr_w(addr, d):
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sim.wr(dut.bank.description[addr].field.storage, d)
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hres = 4
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vres = 4
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csr_w(1, hres) # hres
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csr_w(2, hres+3) # hsync_start
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csr_w(3, hres+5) # hsync_stop
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csr_w(4, hres+10) # hscan
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csr_w(5, vres) # vres
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csr_w(6, vres+3) # vsync_start
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csr_w(7, vres+5) # vsync_stop
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csr_w(8, vres+10) # vscan
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csr_w(10, hres*vres*4) # length
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csr_w(0, 1) # enable
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sim.run(1000)
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main()
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