66 lines
1.8 KiB
Python
66 lines
1.8 KiB
Python
from liteeth.common import *
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class LiteEthPHYGMIITX(Module):
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def __init__(self, pads):
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self.sink = sink = Sink(eth_description(8))
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###
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self.sync += [
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pads.tx_er.eq(0),
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pads.tx_en.eq(sink.stb),
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pads.tx_data.eq(sink.d)
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]
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self.comb += sink.ack.eq(1)
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class LiteEthPHYGMIIRX(Module):
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def __init__(self, pads):
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self.source = source = Source(eth_description(8))
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###
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dv_d = Signal()
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self.sync += dv_d.eq(pads.dv)
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sop = Signal()
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eop = Signal()
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self.comb += [
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sop.eq(pads.dv & ~dv_d),
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eop.eq(~pads.dv & dv_d)
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]
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self.sync += [
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source.stb.eq(pads.dv),
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source.sop.eq(sop),
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source.d.eq(pads.rx_data)
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]
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self.comb += source.eop.eq(eop)
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# CRG is the only Xilinx specific module.
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# TODO: use generic code or add support for others vendors
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class LiteEthPHYGMIICRG(Module, AutoCSR):
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def __init__(self, clock_pads, pads):
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self._reset = CSRStorage()
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###
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.specials += [
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Instance("ODDR",
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p_DDR_CLK_EDGE="SAME_EDGE",
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i_C=ClockSignal("eth_tx"), i_CE=1, i_S=0, i_R=0,
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i_D1=1, i_D2=0, o_Q=clock_pads.gtx,
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),
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Instance("BUFG", i_I=clock_pads.rx, o_O=self.cd_eth_rx.clk),
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]
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self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk)
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reset = self._reset.storage
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self.comb += pads.rst_n.eq(~reset)
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self.specials += [
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AsyncResetSynchronizer(self.cd_eth_tx, reset),
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AsyncResetSynchronizer(self.cd_eth_rx, reset),
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]
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class LiteEthPHYMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads):
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self.dw = 8
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self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads)
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self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads), "eth_tx")
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self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads), "eth_rx")
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self.sink, self.source = self.tx.sink, self.rx.source
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