Sebastien Bourdeauducq 0999a17319 verilog, sim: accept iterables in FHDL statements		2015-10-19 19:17:26 +08:00
..
build	build/vivado: quote paths in Tcl (prevents problems with \ on Windows)	2015-10-19 09:40:44 +08:00
fhdl	verilog, sim: accept iterables in FHDL statements	2015-10-19 19:17:26 +08:00
genlib	genlib/fsm: fix return value of _get_register_control	2015-10-19 19:03:43 +08:00
sim	verilog, sim: accept iterables in FHDL statements	2015-10-19 19:17:26 +08:00
test	test/divider: subtests	2015-10-13 18:39:41 +08:00
util	build: cleanup	2015-09-28 20:34:35 +08:00
__init__.py	simplify imports, migen.fhdl.std -> migen	2015-09-12 19:34:07 +08:00