62 lines
1.6 KiB
Python
62 lines
1.6 KiB
Python
import os
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from migen.fhdl.std import *
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from migen.bus import wishbone
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class LM32(Module):
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def __init__(self, platform, eba_reset):
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self.ibus = i = wishbone.Interface()
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self.dbus = d = wishbone.Interface()
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self.interrupt = Signal(32)
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###
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i_adr_o = Signal(32)
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d_adr_o = Signal(32)
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self.specials += Instance("lm32_cpu",
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p_eba_reset=Instance.PreformattedParam("32'h{:08x}".format(eba_reset)),
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i_clk_i=ClockSignal(),
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i_rst_i=ResetSignal(),
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i_interrupt=self.interrupt,
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o_I_ADR_O=i_adr_o,
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o_I_DAT_O=i.dat_w,
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o_I_SEL_O=i.sel,
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o_I_CYC_O=i.cyc,
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o_I_STB_O=i.stb,
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o_I_WE_O=i.we,
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o_I_CTI_O=i.cti,
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o_I_BTE_O=i.bte,
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i_I_DAT_I=i.dat_r,
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i_I_ACK_I=i.ack,
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i_I_ERR_I=i.err,
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i_I_RTY_I=0,
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o_D_ADR_O=d_adr_o,
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o_D_DAT_O=d.dat_w,
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o_D_SEL_O=d.sel,
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o_D_CYC_O=d.cyc,
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o_D_STB_O=d.stb,
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o_D_WE_O=d.we,
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o_D_CTI_O=d.cti,
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o_D_BTE_O=d.bte,
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i_D_DAT_I=d.dat_r,
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i_D_ACK_I=d.ack,
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i_D_ERR_I=d.err,
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i_D_RTY_I=0)
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self.comb += [
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self.ibus.adr.eq(i_adr_o[2:]),
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self.dbus.adr.eq(d_adr_o[2:])
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]
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# add Verilog sources
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platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"),
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"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
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"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
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"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
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"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
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"lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
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platform.add_verilog_include_path(os.path.join("extcores", "lm32")) |