Sebastien Bourdeauducq f5ab734bdf fhdl/verilog: fix case value sort		2015-09-17 08:03:48 +08:00
..
build	simplify imports, migen.fhdl.std -> migen	2015-09-12 19:34:07 +08:00
fhdl	fhdl/verilog: fix case value sort	2015-09-17 08:03:48 +08:00
genlib	genlib: remove reverse_bytes, FlipFlop, Counter	2015-09-12 19:40:29 +08:00
test	simplify imports, migen.fhdl.std -> migen	2015-09-12 19:34:07 +08:00
util	global: pep8 (E302)	2015-04-13 20:45:35 +02:00
__init__.py	simplify imports, migen.fhdl.std -> migen	2015-09-12 19:34:07 +08:00
sim.py	fhdl/structure: introduce Constant, autowrap for eq/ops, fix Signal as dictionary key problem	2015-09-15 12:38:02 +08:00