111 lines
3.5 KiB
Python
111 lines
3.5 KiB
Python
from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect.stream import *
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from misoc.cores.liteeth_mini.common import *
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def converter_description(dw):
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payload_layout = [("data", dw)]
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return EndpointDescription(payload_layout, packetized=True)
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class LiteEthPHYMIITX(Module):
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def __init__(self, pads, pads_register=True):
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self.sink = sink = Sink(eth_phy_description(8))
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# # #
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if hasattr(pads, "tx_er"):
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self.sync += pads.tx_er.eq(0)
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converter = Converter(converter_description(8),
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converter_description(4))
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self.submodules += converter
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self.comb += [
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converter.sink.stb.eq(sink.stb),
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converter.sink.data.eq(sink.data),
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sink.ack.eq(converter.sink.ack),
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converter.source.ack.eq(1)
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]
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pads_eq = [
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pads.tx_en.eq(converter.source.stb),
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pads.tx_data.eq(converter.source.data)
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]
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if pads_register:
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self.sync += pads_eq
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else:
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self.comb += pads_eq
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class LiteEthPHYMIIRX(Module):
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def __init__(self, pads):
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self.source = source = Source(eth_phy_description(8))
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# # #
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sop = Signal(reset=1)
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sop_set = Signal()
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sop_clr = Signal()
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self.sync += If(sop_set, sop.eq(1)).Elif(sop_clr, sop.eq(0))
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converter = Converter(converter_description(4),
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converter_description(8))
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converter = ResetInserter()(converter)
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self.submodules += converter
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self.sync += [
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converter.reset.eq(~pads.dv),
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converter.sink.stb.eq(1),
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converter.sink.data.eq(pads.rx_data)
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]
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self.sync += [
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sop_set.eq(~pads.dv),
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sop_clr.eq(pads.dv)
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]
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self.comb += [
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converter.sink.sop.eq(sop),
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converter.sink.eop.eq(~pads.dv)
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]
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self.comb += Record.connect(converter.source, source)
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class LiteEthPHYMIICRG(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset):
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self._reset = CSRStorage()
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# # #
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if hasattr(clock_pads, "phy"):
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self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
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self.comb += self.cd_eth_tx.clk.eq(clock_pads.tx)
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if with_hw_init_reset:
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reset = Signal()
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counter_done = Signal()
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self.submodules.counter = counter = Counter(max=512)
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self.comb += [
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counter_done.eq(counter.value == 256),
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counter.ce.eq(~counter_done),
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reset.eq(~counter_done | self._reset.storage)
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]
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else:
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reset = self._reset.storage
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self.comb += pads.rst_n.eq(~reset)
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self.specials += [
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AsyncResetSynchronizer(self.cd_eth_tx, reset),
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AsyncResetSynchronizer(self.cd_eth_rx, reset),
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]
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class LiteEthPHYMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True):
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self.dw = 8
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self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIITX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIIRX(pads))
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self.sink, self.source = self.tx.sink, self.rx.source
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