634 lines
20 KiB
Python
634 lines
20 KiB
Python
from functools import reduce
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from operator import or_
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from migen import *
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from migen.genlib import roundrobin
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from migen.genlib.record import *
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from migen.genlib.misc import split, displacer, chooser
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from migen.genlib.fsm import FSM, NextState
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from misoc.interconnect import csr
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# TODO: rewrite without FlipFlop and Counter
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_layout = [
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("adr", 30, DIR_M_TO_S),
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("dat_w", "data_width", DIR_M_TO_S),
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("dat_r", "data_width", DIR_S_TO_M),
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("sel", "sel_width", DIR_M_TO_S),
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("cyc", 1, DIR_M_TO_S),
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M),
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("we", 1, DIR_M_TO_S),
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("cti", 3, DIR_M_TO_S),
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("bte", 2, DIR_M_TO_S),
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("err", 1, DIR_S_TO_M)
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]
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class Interface(Record):
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def __init__(self, data_width=32):
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Record.__init__(self, set_layout_parameters(_layout,
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data_width=data_width,
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sel_width=data_width//8))
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class InterconnectPointToPoint(Module):
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def __init__(self, master, slave):
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self.comb += master.connect(slave)
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class Arbiter(Module):
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def __init__(self, masters, target):
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self.submodules.rr = roundrobin.RoundRobin(len(masters))
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# mux master->slave signals
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for name, size, direction in _layout:
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if direction == DIR_M_TO_S:
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choices = Array(getattr(m, name) for m in masters)
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self.comb += getattr(target, name).eq(choices[self.rr.grant])
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# connect slave->master signals
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for name, size, direction in _layout:
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if direction == DIR_S_TO_M:
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source = getattr(target, name)
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for i, m in enumerate(masters):
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dest = getattr(m, name)
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if name == "ack" or name == "err":
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self.comb += dest.eq(source & (self.rr.grant == i))
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else:
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self.comb += dest.eq(source)
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# connect bus requests to round-robin selector
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reqs = [m.cyc for m in masters]
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self.comb += self.rr.request.eq(Cat(*reqs))
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class Decoder(Module):
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# slaves is a list of pairs:
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# 0) function that takes the address signal and returns a FHDL expression
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# that evaluates to 1 when the slave is selected and 0 otherwise.
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# 1) wishbone.Slave reference.
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# register adds flip-flops after the address comparators. Improves timing,
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# but breaks Wishbone combinatorial feedback.
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def __init__(self, master, slaves, register=False):
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ns = len(slaves)
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slave_sel = Signal(ns)
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slave_sel_r = Signal(ns)
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# decode slave addresses
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self.comb += [slave_sel[i].eq(fun(master.adr))
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for i, (fun, bus) in enumerate(slaves)]
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if register:
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self.sync += slave_sel_r.eq(slave_sel)
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else:
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self.comb += slave_sel_r.eq(slave_sel)
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# connect master->slaves signals except cyc
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for slave in slaves:
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for name, size, direction in _layout:
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if direction == DIR_M_TO_S and name != "cyc":
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self.comb += getattr(slave[1], name).eq(getattr(master, name))
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# combine cyc with slave selection signals
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self.comb += [slave[1].cyc.eq(master.cyc & slave_sel[i])
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for i, slave in enumerate(slaves)]
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# generate master ack (resp. err) by ORing all slave acks (resp. errs)
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self.comb += [
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master.ack.eq(reduce(or_, [slave[1].ack for slave in slaves])),
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master.err.eq(reduce(or_, [slave[1].err for slave in slaves]))
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]
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# mux (1-hot) slave data return
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masked = [Replicate(slave_sel_r[i], len(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
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self.comb += master.dat_r.eq(reduce(or_, masked))
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class InterconnectShared(Module):
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def __init__(self, masters, slaves, register=False):
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shared = Interface()
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self.submodules += Arbiter(masters, shared)
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self.submodules += Decoder(shared, slaves, register)
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class Crossbar(Module):
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def __init__(self, masters, slaves, register=False):
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matches, busses = zip(*slaves)
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access = [[Interface() for j in slaves] for i in masters]
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# decode each master into its access row
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for row, master in zip(access, masters):
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row = list(zip(matches, row))
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self.submodules += Decoder(master, row, register)
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# arbitrate each access column onto its slave
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for column, bus in zip(zip(*access), busses):
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self.submodules += Arbiter(column, bus)
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class DownConverter(Module):
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"""DownConverter
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This module splits Wishbone accesses from a master interface to a smaller
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slave interface.
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Writes:
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Writes from master are splitted N writes to the slave. Access is acked when the last
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access is acked by the slave.
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Reads:
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Read from master are splitted in N reads to the the slave. Read datas from
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the slave are cached before being presented concatenated on the last access.
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TODO:
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Manage err signal? (Not implemented since we generally don't use it on Migen/MiSoC modules)
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"""
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def __init__(self, master, slave):
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dw_from = len(master.dat_r)
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dw_to = len(slave.dat_w)
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ratio = dw_from//dw_to
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# # #
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read = Signal()
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write = Signal()
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counter = Counter(max=ratio)
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self.submodules += counter
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counter_done = Signal()
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self.comb += counter_done.eq(counter.value == ratio-1)
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# Main FSM
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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counter.reset.eq(1),
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If(master.stb & master.cyc,
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If(master.we,
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NextState("WRITE")
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).Else(
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NextState("READ")
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)
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)
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)
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fsm.act("WRITE",
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write.eq(1),
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slave.we.eq(1),
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slave.cyc.eq(1),
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If(master.stb & master.cyc,
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slave.stb.eq(1),
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If(slave.ack,
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counter.ce.eq(1),
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If(counter_done,
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master.ack.eq(1),
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NextState("IDLE")
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)
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)
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).Elif(~master.cyc,
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NextState("IDLE")
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)
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)
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fsm.act("READ",
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read.eq(1),
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slave.cyc.eq(1),
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If(master.stb & master.cyc,
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slave.stb.eq(1),
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If(slave.ack,
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counter.ce.eq(1),
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If(counter_done,
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master.ack.eq(1),
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NextState("IDLE")
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)
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)
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).Elif(~master.cyc,
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NextState("IDLE")
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)
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)
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# Address
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self.comb += [
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If(counter_done,
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slave.cti.eq(7) # indicate end of burst
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).Else(
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slave.cti.eq(2)
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),
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slave.adr.eq(Cat(counter.value, master.adr))
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]
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# Datapath
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cases = {}
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for i in range(ratio):
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cases[i] = [
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slave.sel.eq(master.sel[i*dw_to//8:(i+1)*dw_to]),
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slave.dat_w.eq(master.dat_w[i*dw_to:(i+1)*dw_to])
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]
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self.comb += Case(counter.value, cases)
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cached_data = Signal(dw_from)
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self.comb += master.dat_r.eq(Cat(cached_data[dw_to:], slave.dat_r))
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self.sync += \
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If(read & counter.ce,
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cached_data.eq(master.dat_r)
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)
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class UpConverter(Module):
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"""UpConverter
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This module up-converts wishbone accesses and bursts from a master interface
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to a wider slave interface. This allows efficient use wishbone bursts.
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Writes:
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Wishbone writes are cached before being written to the slave. Access to
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the slave is done at the end of a burst or when address reach end of burst
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addressing.
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Reads:
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Cache is refilled only at the beginning of each burst, the subsequent
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reads of a burst use the cached data.
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TODO:
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Manage err signal? (Not implemented since we generally don't use it on Migen/MiSoC modules)
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"""
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def __init__(self, master, slave):
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dw_from = len(master.dat_r)
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dw_to = len(slave.dat_w)
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ratio = dw_to//dw_from
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ratiobits = log2_int(ratio)
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# # #
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write = Signal()
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evict = Signal()
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refill = Signal()
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read = Signal()
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address = FlipFlop(30)
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self.submodules += address
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self.comb += address.d.eq(master.adr)
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counter = Counter(max=ratio)
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self.submodules += counter
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counter_offset = Signal(max=ratio)
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counter_done = Signal()
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self.comb += [
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counter_offset.eq(address.q),
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counter_done.eq((counter.value + counter_offset) == ratio-1)
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]
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cached_data = Signal(dw_to)
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cached_sel = Signal(dw_to//8)
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end_of_burst = Signal()
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self.comb += end_of_burst.eq(~master.cyc |
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(master.stb & master.cyc & master.ack & ((master.cti == 7) | counter_done)))
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need_refill = FlipFlop(reset=1)
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self.submodules += need_refill
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self.comb += [
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need_refill.reset.eq(end_of_burst),
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need_refill.d.eq(0)
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]
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# Main FSM
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self.submodules.fsm = fsm = FSM()
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fsm.act("IDLE",
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counter.reset.eq(1),
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If(master.stb & master.cyc,
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address.ce.eq(1),
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If(master.we,
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NextState("WRITE")
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).Else(
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If(need_refill.q,
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NextState("REFILL")
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).Else(
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NextState("READ")
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)
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)
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)
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)
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fsm.act("WRITE",
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If(master.stb & master.cyc,
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write.eq(1),
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counter.ce.eq(1),
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master.ack.eq(1),
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If(counter_done,
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NextState("EVICT")
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)
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).Elif(~master.cyc,
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NextState("EVICT")
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)
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)
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fsm.act("EVICT",
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evict.eq(1),
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slave.stb.eq(1),
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slave.we.eq(1),
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slave.cyc.eq(1),
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slave.dat_w.eq(cached_data),
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slave.sel.eq(cached_sel),
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If(slave.ack,
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NextState("IDLE")
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)
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)
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fsm.act("REFILL",
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refill.eq(1),
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slave.stb.eq(1),
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slave.cyc.eq(1),
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If(slave.ack,
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need_refill.ce.eq(1),
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NextState("READ")
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)
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)
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fsm.act("READ",
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read.eq(1),
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If(master.stb & master.cyc,
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master.ack.eq(1)
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),
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NextState("IDLE")
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)
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# Address
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self.comb += [
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slave.cti.eq(7), # we are not able to generate bursts since up-converting
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slave.adr.eq(address.q[ratiobits:])
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]
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# Datapath
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cached_datas = [FlipFlop(dw_from) for i in range(ratio)]
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cached_sels = [FlipFlop(dw_from//8) for i in range(ratio)]
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self.submodules += cached_datas, cached_sels
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cases = {}
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for i in range(ratio):
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write_sel = Signal()
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cases[i] = write_sel.eq(1)
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self.comb += [
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cached_sels[i].reset.eq(counter.reset),
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If(write,
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cached_datas[i].d.eq(master.dat_w),
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).Else(
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cached_datas[i].d.eq(slave.dat_r[dw_from*i:dw_from*(i+1)])
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),
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cached_sels[i].d.eq(master.sel),
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If((write & write_sel) | refill,
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cached_datas[i].ce.eq(1),
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cached_sels[i].ce.eq(1)
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)
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]
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self.comb += Case(counter.value + counter_offset, cases)
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cases = {}
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for i in range(ratio):
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cases[i] = master.dat_r.eq(cached_datas[i].q)
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self.comb += Case(address.q[:ratiobits], cases)
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self.comb += [
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cached_data.eq(Cat([cached_data.q for cached_data in cached_datas])),
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cached_sel.eq(Cat([cached_sel.q for cached_sel in cached_sels]))
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]
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class Converter(Module):
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"""Converter
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This module is a wrapper for DownConverter and UpConverter.
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It should preferably be used rather than direct instantiations
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of specific converters.
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"""
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def __init__(self, master, slave):
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self.master = master
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self.slave = slave
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# # #
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dw_from = len(master.dat_r)
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dw_to = len(slave.dat_r)
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if dw_from > dw_to:
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downconverter = DownConverter(master, slave)
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self.submodules += downconverter
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elif dw_from < dw_to:
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upconverter = UpConverter(master, slave)
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self.submodules += upconverter
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else:
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Record.connect(master, slave)
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class Cache(Module):
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"""Cache
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This module is a write-back wishbone cache that can be used as a L2 cache.
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Cachesize (in 32-bit words) is the size of the data store and must be a power of 2
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"""
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def __init__(self, cachesize, master, slave):
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self.master = master
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self.slave = slave
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###
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dw_from = len(master.dat_r)
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dw_to = len(slave.dat_r)
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if dw_to > dw_from and (dw_to % dw_from) != 0:
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raise ValueError("Slave data width must be a multiple of {dw}".format(dw=dw_from))
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if dw_to < dw_from and (dw_from % dw_to) != 0:
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raise ValueError("Master data width must be a multiple of {dw}".format(dw=dw_to))
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# Split address:
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# TAG | LINE NUMBER | LINE OFFSET
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offsetbits = log2_int(max(dw_to//dw_from, 1))
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addressbits = len(slave.adr) + offsetbits
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linebits = log2_int(cachesize) - offsetbits
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tagbits = addressbits - linebits
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wordbits = log2_int(max(dw_from//dw_to, 1))
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adr_offset, adr_line, adr_tag = split(master.adr, offsetbits, linebits, tagbits)
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word = Signal(wordbits) if wordbits else None
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# Data memory
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data_mem = Memory(dw_to*2**wordbits, 2**linebits)
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data_port = data_mem.get_port(write_capable=True, we_granularity=8)
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self.specials += data_mem, data_port
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write_from_slave = Signal()
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if adr_offset is None:
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adr_offset_r = None
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else:
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adr_offset_r = Signal(offsetbits)
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self.sync += adr_offset_r.eq(adr_offset)
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self.comb += [
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data_port.adr.eq(adr_line),
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If(write_from_slave,
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displacer(slave.dat_r, word, data_port.dat_w),
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displacer(Replicate(1, dw_to//8), word, data_port.we)
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).Else(
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data_port.dat_w.eq(Replicate(master.dat_w, max(dw_to//dw_from, 1))),
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If(master.cyc & master.stb & master.we & master.ack,
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displacer(master.sel, adr_offset, data_port.we, 2**offsetbits, reverse=True)
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)
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),
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chooser(data_port.dat_r, word, slave.dat_w),
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slave.sel.eq(2**(dw_to//8)-1),
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chooser(data_port.dat_r, adr_offset_r, master.dat_r, reverse=True)
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]
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# Tag memory
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tag_layout = [("tag", tagbits), ("dirty", 1)]
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tag_mem = Memory(layout_len(tag_layout), 2**linebits)
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tag_port = tag_mem.get_port(write_capable=True)
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self.specials += tag_mem, tag_port
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tag_do = Record(tag_layout)
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tag_di = Record(tag_layout)
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self.comb += [
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tag_do.raw_bits().eq(tag_port.dat_r),
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tag_port.dat_w.eq(tag_di.raw_bits())
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]
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self.comb += [
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tag_port.adr.eq(adr_line),
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tag_di.tag.eq(adr_tag)
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]
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if word is not None:
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self.comb += slave.adr.eq(Cat(word, adr_line, tag_do.tag))
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else:
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self.comb += slave.adr.eq(Cat(adr_line, tag_do.tag))
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# slave word computation, word_clr and word_inc will be simplified
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# at synthesis when wordbits=0
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word_clr = Signal()
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word_inc = Signal()
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if word is not None:
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self.sync += \
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If(word_clr,
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word.eq(0),
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).Elif(word_inc,
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word.eq(word+1)
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)
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def word_is_last(word):
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if word is not None:
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return word == 2**wordbits-1
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else:
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return 1
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# Control FSM
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
|
|
fsm.act("IDLE",
|
|
If(master.cyc & master.stb,
|
|
NextState("TEST_HIT")
|
|
)
|
|
)
|
|
fsm.act("TEST_HIT",
|
|
word_clr.eq(1),
|
|
If(tag_do.tag == adr_tag,
|
|
master.ack.eq(1),
|
|
If(master.we,
|
|
tag_di.dirty.eq(1),
|
|
tag_port.we.eq(1)
|
|
),
|
|
NextState("IDLE")
|
|
).Else(
|
|
If(tag_do.dirty,
|
|
NextState("EVICT")
|
|
).Else(
|
|
NextState("REFILL_WRTAG")
|
|
)
|
|
)
|
|
)
|
|
|
|
fsm.act("EVICT",
|
|
slave.stb.eq(1),
|
|
slave.cyc.eq(1),
|
|
slave.we.eq(1),
|
|
If(slave.ack,
|
|
word_inc.eq(1),
|
|
If(word_is_last(word),
|
|
NextState("REFILL_WRTAG")
|
|
)
|
|
)
|
|
)
|
|
fsm.act("REFILL_WRTAG",
|
|
# Write the tag first to set the slave address
|
|
tag_port.we.eq(1),
|
|
word_clr.eq(1),
|
|
NextState("REFILL")
|
|
)
|
|
fsm.act("REFILL",
|
|
slave.stb.eq(1),
|
|
slave.cyc.eq(1),
|
|
slave.we.eq(0),
|
|
If(slave.ack,
|
|
write_from_slave.eq(1),
|
|
word_inc.eq(1),
|
|
If(word_is_last(word),
|
|
NextState("TEST_HIT"),
|
|
).Else(
|
|
NextState("REFILL")
|
|
)
|
|
)
|
|
)
|
|
|
|
|
|
class SRAM(Module):
|
|
def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
|
|
if bus is None:
|
|
bus = Interface()
|
|
self.bus = bus
|
|
bus_data_width = len(self.bus.dat_r)
|
|
if isinstance(mem_or_size, Memory):
|
|
assert(mem_or_size.width <= bus_data_width)
|
|
self.mem = mem_or_size
|
|
else:
|
|
self.mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)
|
|
if read_only is None:
|
|
if hasattr(self.mem, "bus_read_only"):
|
|
read_only = self.mem.bus_read_only
|
|
else:
|
|
read_only = False
|
|
|
|
###
|
|
|
|
# memory
|
|
port = self.mem.get_port(write_capable=not read_only, we_granularity=8)
|
|
self.specials += self.mem, port
|
|
# generate write enable signal
|
|
if not read_only:
|
|
self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
|
|
for i in range(4)]
|
|
# address and data
|
|
self.comb += [
|
|
port.adr.eq(self.bus.adr[:len(port.adr)]),
|
|
self.bus.dat_r.eq(port.dat_r)
|
|
]
|
|
if not read_only:
|
|
self.comb += port.dat_w.eq(self.bus.dat_w),
|
|
# generate ack
|
|
self.sync += [
|
|
self.bus.ack.eq(0),
|
|
If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1))
|
|
]
|
|
|
|
|
|
class CSRBank(csr.GenericBank):
|
|
def __init__(self, description, bus=None):
|
|
if bus is None:
|
|
bus = Interface()
|
|
self.bus = bus
|
|
|
|
###
|
|
|
|
GenericBank.__init__(self, description, len(self.bus.dat_w))
|
|
|
|
for i, c in enumerate(self.simple_csrs):
|
|
self.comb += [
|
|
c.r.eq(self.bus.dat_w[:c.size]),
|
|
c.re.eq(self.bus.cyc & self.bus.stb & ~self.bus.ack & self.bus.we & \
|
|
(self.bus.adr[:self.decode_bits] == i))
|
|
]
|
|
|
|
brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(self.simple_csrs))
|
|
self.sync += [
|
|
Case(self.bus.adr[:self.decode_bits], brcases),
|
|
If(bus.ack, bus.ack.eq(0)).Elif(bus.cyc & bus.stb, bus.ack.eq(1))
|
|
]
|