60 lines
1.7 KiB
Python
60 lines
1.7 KiB
Python
import unittest
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import os
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from migen import *
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from litex.soc.integration.builder import *
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def build_test(socs):
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errors = 0
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for soc in socs:
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os.system("rm -rf build")
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builder = Builder(soc, output_dir="./build", compile_software=False, compile_gateware=False)
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builder.build()
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errors += not os.path.isfile("./build/gateware/top.v")
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os.system("rm -rf build")
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return errors
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class TestTargets(unittest.TestCase):
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# altera boards
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def test_de0nano(self):
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from litex.boards.targets.de0nano import BaseSoC
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errors = build_test([BaseSoC()])
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self.assertEqual(errors, 0)
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# xilinx boards
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def test_minispartan6(self):
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from litex.boards.targets.minispartan6 import BaseSoC
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errors = build_test([BaseSoC()])
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self.assertEqual(errors, 0)
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def test_arty(self):
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from litex.boards.targets.arty import BaseSoC, EthernetSoC
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errors = build_test([BaseSoC(), EthernetSoC()])
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self.assertEqual(errors, 0)
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def test_nexys4ddr(self):
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from litex.boards.targets.nexys4ddr import BaseSoC
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errors = build_test([BaseSoC()])
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self.assertEqual(errors, 0)
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def test_nexys_video(self):
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from litex.boards.targets.nexys_video import BaseSoC, EthernetSoC
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errors = build_test([BaseSoC(), EthernetSoC()])
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self.assertEqual(errors, 0)
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def test_genesys2(self):
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from litex.boards.targets.genesys2 import BaseSoC, EthernetSoC
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errors = build_test([BaseSoC(), EthernetSoC()])
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self.assertEqual(errors, 0)
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def test_kc705(self):
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from litex.boards.targets.kc705 import BaseSoC, EthernetSoC
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errors = build_test([BaseSoC(), EthernetSoC()])
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self.assertEqual(errors, 0)
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# lattice boards
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