126 lines
2.8 KiB
Python
126 lines
2.8 KiB
Python
from fractions import Fraction
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from math import ceil
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
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from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon
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import constraints
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MHz = 1000000
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clk_freq = (83 + Fraction(1, 3))*MHz
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sram_size = 4096 # in bytes
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l2_size = 8192 # in bytes
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clk_period_ns = 1000000000/clk_freq
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def ns(t, margin=True):
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if margin:
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t += clk_period_ns/2
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return ceil(t/clk_period_ns)
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sdram_phy = asmicon.PhySettings(
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dfi_d=64,
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nphases=2,
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rdphase=0,
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wrphase=1
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)
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sdram_geom = asmicon.GeomSettings(
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bank_a=2,
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row_a=13,
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col_a=10
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)
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sdram_timing = asmicon.TimingSettings(
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tRP=ns(15),
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tRCD=ns(15),
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tREFI=ns(7800, False),
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tRFC=ns(70),
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slot_time=16
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)
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def ddrphy_clocking(crg, phy):
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names = [
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"clk2x_270",
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"clk4x_wr",
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"clk4x_wr_strb",
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"clk4x_rd",
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"clk4x_rd_strb"
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]
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comb = [getattr(phy, name).eq(getattr(crg, name)) for name in names]
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return Fragment(comb)
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def get():
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#
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# ASMI
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#
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asmicon0 = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
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asmiport_wb = asmicon0.hub.get_port()
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asmicon0.finalize()
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#
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# DFI
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#
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ddrphy0 = s6ddrphy.S6DDRPHY(sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d)
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dfii0 = dfii.DFIInjector(1, sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d, sdram_phy.nphases)
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dficon0 = dfi.Interconnect(dfii0.master, ddrphy0.dfi)
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dficon1 = dfi.Interconnect(asmicon0.dfi, dfii0.slave)
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#
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# WISHBONE
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#
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cpu0 = lm32.LM32()
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norflash0 = norflash.NorFlash(25, 12)
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sram0 = sram.SRAM(sram_size//4)
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wishbone2asmi0 = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
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wishbone2csr0 = wishbone2csr.WB2CSR()
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# norflash 0x00000000 (shadow @0x80000000)
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# SRAM/debug 0x10000000 (shadow @0x90000000)
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# USB 0x20000000 (shadow @0xa0000000)
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# Ethernet 0x30000000 (shadow @0xb0000000)
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# SDRAM 0x40000000 (shadow @0xc0000000)
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# CSR bridge 0x60000000 (shadow @0xe0000000)
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wishbonecon0 = wishbone.InterconnectShared(
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[
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cpu0.ibus,
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cpu0.dbus
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], [
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(binc("000"), norflash0.bus),
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(binc("001"), sram0.bus),
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(binc("10"), wishbone2asmi0.wishbone),
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(binc("11"), wishbone2csr0.wishbone)
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],
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register=True,
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offset=1)
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#
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# CSR
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#
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uart0 = uart.UART(0, clk_freq, baud=115200)
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csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
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uart0.bank.interface,
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dfii0.bank.interface
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])
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#
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# Interrupts
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#
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interrupts = Fragment([
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cpu0.interrupt[0].eq(uart0.events.irq)
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])
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#
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# Housekeeping
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#
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crg0 = m1crg.M1CRG(50*MHz, clk_freq)
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frag = autofragment.from_local() + interrupts + ddrphy_clocking(crg0, ddrphy0)
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src_verilog, vns = verilog.convert(frag,
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{crg0.trigger_reset},
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name="soc",
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clk_signal=crg0.sys_clk,
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rst_signal=crg0.sys_rst,
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return_ns=True)
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src_ucf = constraints.get(vns, crg0, norflash0, uart0, ddrphy0)
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return (src_verilog, src_ucf)
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