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https://github.com/enjoy-digital/litex.git
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0e00837f42
litex
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verilog
History
Sebastien Bourdeauducq
7b14e0bd05
asmicon: skeleton
2012-03-14 18:26:05 +01:00
..
lm32
LM32: make IP read-only and interrupt lines level-sensitive
2012-02-07 00:07:12 +01:00
m1crg
s6ddrphy: write path OK in simulation
2012-02-20 23:55:20 +01:00
s6ddrphy
asmicon: skeleton
2012-03-14 18:26:05 +01:00