Sebastien Bourdeauducq 0e195da3c0 bank/csrgen: add get_offset function to pre-calculate register addresses		2013-08-02 23:05:54 +02:00
..
actorlib	actorlib/spi: remove unused function	2013-07-27 15:36:42 +02:00
bank	bank/csrgen: add get_offset function to pre-calculate register addresses	2013-08-02 23:05:54 +02:00
bus	csr: new data width API	2013-07-28 16:33:36 +02:00
fhdl	fhdl: add EDIF back-end	2013-07-31 22:47:43 +02:00
flow	flow/actor/PipelinedActor: clean up	2013-07-12 18:52:34 +02:00
genlib	genlib/record: support abstract signal width	2013-07-27 22:18:06 +02:00
pytholite	pytholite/io: len -> flen	2013-07-27 15:38:48 +02:00
sim	fhdl: do not export Fragment	2013-07-25 18:52:54 +02:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00