litex/verilog
Sebastien Bourdeauducq 411e1af980 Proper reset generation 2011-12-16 22:25:26 +01:00
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lm32 Initial import 2011-12-13 17:33:12 +01:00
m1reset Proper reset generation 2011-12-16 22:25:26 +01:00
uart Initial import 2011-12-13 17:33:12 +01:00