Sebastien Bourdeauducq b862b070d6 fhdl/verilog: recursive Special lowering		2013-04-25 14:56:26 +02:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
module.py	fhdl/module/finalize: pass additional args to do_finalize	2013-03-30 11:29:46 +01:00
namer.py	New 'specials' API	2013-02-22 17:56:35 +01:00
specials.py	fhdl/specials/memory: do not write address register for async reads	2013-04-25 13:30:05 +02:00
structure.py	Support for resetless clock domains	2013-04-23 11:54:05 +02:00
tools.py	Support for resetless clock domains	2013-04-23 11:54:05 +02:00
tracer.py	bank: automatic register naming	2013-03-12 15:45:24 +01:00
verilog.py	fhdl/verilog: recursive Special lowering	2013-04-25 14:56:26 +02:00
visit.py	fhdl/visit: add TransformModule	2013-04-10 23:42:14 +02:00