26 lines
399 B
Python
26 lines
399 B
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog
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dx = 5
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dy = 5
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x = Signal(BV(bits_for(dx-1)))
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y = Signal(BV(bits_for(dy-1)))
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out = Signal()
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my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy))
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comb = [
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out.eq(my_2d_array[x][y])
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]
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we = Signal()
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inp = Signal()
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sync = [
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If(we,
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my_2d_array[x][y].eq(inp)
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)
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]
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f = Fragment(comb)
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print(verilog.convert(f))
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