litex/targets
Florent Kermarrec 711540e15c targets/mlabs_video: rename sdram_module to sdram_modules to reflect that we have 2 modules sharing the same characteristics 2015-03-21 18:10:56 +01:00
..
__init__.py add support for external platforms and targets 2013-11-24 16:55:33 +01:00
de0nano.py sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets 2015-03-21 16:56:53 +01:00
kc705.py targets/kc705: rename sdram_module to sdram_modules to reflect that we have 8 modules sharing the same characteristics 2015-03-21 18:07:10 +01:00
mlabs_video.py targets/mlabs_video: rename sdram_module to sdram_modules to reflect that we have 2 modules sharing the same characteristics 2015-03-21 18:10:56 +01:00
pipistrello.py sdram: define MT46V32M16/MT8JTF12864 and use it on pipistrello/kc705 2015-03-21 17:25:36 +01:00
ppro.py sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets 2015-03-21 16:56:53 +01:00
simple.py targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains) 2015-03-17 01:07:44 +01:00
versa.py targets: add Lattice ECP3 versa 2015-03-17 19:09:43 +01:00