20 lines
638 B
Python
20 lines
638 B
Python
from migen.fhdl.structure import *
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from migen.fhdl.specials import SynthesisDirective
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from migen.fhdl import verilog
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from migen.genlib.cdc import *
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class XilinxMultiRegImpl(MultiRegImpl):
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def get_fragment(self):
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disable_srl = set(SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
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for r in self.regs)
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return MultiRegImpl.get_fragment(self) + Fragment(specials=disable_srl)
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class XilinxMultiReg:
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@staticmethod
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def lower(dr):
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return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
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ps = PulseSynchronizer("from", "to")
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v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
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print(v)
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