65 lines
2.1 KiB
Python
65 lines
2.1 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.bus import dfi
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from migen.bank.description import *
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class PhaseInjector(Module, AutoReg):
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def __init__(self, phase):
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self._cs = Field(1, WRITE_ONLY, READ_ONLY)
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self._we = Field(1, WRITE_ONLY, READ_ONLY)
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self._cas = Field(1, WRITE_ONLY, READ_ONLY)
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self._ras = Field(1, WRITE_ONLY, READ_ONLY)
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self._wren = Field(1, WRITE_ONLY, READ_ONLY)
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self._rden = Field(1, WRITE_ONLY, READ_ONLY)
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self._command = RegisterFields(self._cs, self._we, self._cas, self._ras, self._wren, self._rden)
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self._command_issue = RegisterRaw()
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self._address = RegisterField(len(phase.address))
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self._baddress = RegisterField(len(phase.bank))
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self._wrdata = RegisterField(len(phase.wrdata))
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self._rddata = RegisterField(len(phase.rddata), READ_ONLY, WRITE_ONLY)
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###
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self.comb += [
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If(self._command_issue.re,
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phase.cs_n.eq(~self._cs.r),
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phase.we_n.eq(~self._we.r),
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phase.cas_n.eq(~self._cas.r),
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phase.ras_n.eq(~self._ras.r)
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).Else(
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phase.cs_n.eq(1),
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phase.we_n.eq(1),
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phase.cas_n.eq(1),
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phase.ras_n.eq(1)
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),
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phase.address.eq(self._address.field.r),
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phase.bank.eq(self._baddress.field.r),
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phase.wrdata_en.eq(self._command_issue.re & self._wren.r),
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phase.rddata_en.eq(self._command_issue.re & self._rden.r),
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phase.wrdata.eq(self._wrdata.field.r),
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phase.wrdata_mask.eq(0)
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]
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self.sync += If(phase.rddata_valid, self._rddata.field.w.eq(phase.rddata))
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class DFIInjector(Module, AutoReg):
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def __init__(self, a, ba, d, nphases=1):
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inti = dfi.Interface(a, ba, d, nphases)
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self.slave = dfi.Interface(a, ba, d, nphases)
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self.master = dfi.Interface(a, ba, d, nphases)
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self._sel = Field()
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self._cke = Field()
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self._control = RegisterFields(self._sel, self._cke)
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for n, phase in enumerate(inti.phases):
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setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
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###
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connect_inti = dfi.interconnect_stmts(inti, self.master)
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connect_slave = dfi.interconnect_stmts(self.slave, self.master)
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self.comb += If(self._sel.r, *connect_slave).Else(*connect_inti)
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self.comb += [phase.cke.eq(self._cke.r) for phase in inti.phases]
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