135 lines
4.8 KiB
Python
135 lines
4.8 KiB
Python
from migen.fhdl.std import *
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from migen.bus.transactions import *
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from migen.bank.description import CSRStorage
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from migen.genlib.record import *
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from migen.genlib.misc import chooser
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_layout = [
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("adr", "address_width", DIR_M_TO_S),
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("we", 1, DIR_M_TO_S),
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("dat_w", "data_width", DIR_M_TO_S),
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("dat_r", "data_width", DIR_S_TO_M)
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]
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class Interface(Record):
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def __init__(self, data_width=8, address_width=14):
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Record.__init__(self, set_layout_parameters(_layout,
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data_width=data_width, address_width=address_width))
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class Interconnect(Module):
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def __init__(self, master, slaves):
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self.comb += master.connect(*slaves)
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class Initiator(Module):
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def __init__(self, generator, bus=None):
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self.generator = generator
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if bus is None:
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bus = Interface()
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self.bus = bus
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self.transaction = None
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self.read_data_ready = False
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self.done = False
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def do_simulation(self, selfp):
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if not self.done:
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if self.transaction is not None:
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if isinstance(self.transaction, TRead):
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if self.read_data_ready:
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self.transaction.data = selfp.bus.dat_r
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self.transaction = None
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self.read_data_ready = False
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else:
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self.read_data_ready = True
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else:
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selfp.bus.we = 0
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self.transaction = None
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if self.transaction is None:
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try:
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self.transaction = next(self.generator)
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except StopIteration:
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self.transaction = None
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raise StopSimulation
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if self.transaction is not None:
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selfp.bus.adr = self.transaction.address
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if isinstance(self.transaction, TWrite):
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selfp.bus.we = 1
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selfp.bus.dat_w = self.transaction.data
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class SRAM(Module):
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def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
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if bus is None:
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bus = Interface()
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self.bus = bus
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data_width = flen(self.bus.dat_w)
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if isinstance(mem_or_size, Memory):
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mem = mem_or_size
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else:
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mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
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csrw_per_memw = (mem.width + data_width - 1)//data_width
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word_bits = log2_int(csrw_per_memw)
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page_bits = log2_int((mem.depth*csrw_per_memw + 511)//512, False)
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if page_bits:
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self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
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else:
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self._page = None
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if read_only is None:
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if hasattr(mem, "bus_read_only"):
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read_only = mem.bus_read_only
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else:
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read_only = False
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###
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port = mem.get_port(write_capable=not read_only)
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self.specials += mem, port
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sel = Signal()
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sel_r = Signal()
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self.sync += sel_r.eq(sel)
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self.comb += sel.eq(self.bus.adr[9:] == address)
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if word_bits:
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word_index = Signal(word_bits)
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word_expanded = Signal(csrw_per_memw*data_width)
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self.sync += word_index.eq(self.bus.adr[:word_bits])
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self.comb += [
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word_expanded.eq(port.dat_r),
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If(sel_r,
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chooser(word_expanded, word_index, self.bus.dat_r, n=csrw_per_memw, reverse=True)
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)
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]
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if not read_only:
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wregs = []
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for i in range(csrw_per_memw-1):
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wreg = Signal(data_width)
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self.sync += If(sel & self.bus.we & (self.bus.adr[:word_bits] == i), wreg.eq(self.bus.dat_w))
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wregs.append(wreg)
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memword_chunks = [self.bus.dat_w] + list(reversed(wregs))
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self.comb += [
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port.we.eq(sel & self.bus.we & (self.bus.adr[:word_bits] == csrw_per_memw - 1)),
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port.dat_w.eq(Cat(*memword_chunks))
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]
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else:
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self.comb += If(sel_r, self.bus.dat_r.eq(port.dat_r))
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if not read_only:
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self.comb += [
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port.we.eq(sel & self.bus.we),
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port.dat_w.eq(self.bus.dat_w)
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]
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if self._page is None:
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self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+flen(port.adr)])
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else:
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pv = self._page.storage
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self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+flen(port.adr)-flen(pv)], pv))
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def get_csrs(self):
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if self._page is None:
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return []
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else:
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return [self._page]
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