141 lines
3.1 KiB
Python
141 lines
3.1 KiB
Python
from migen.fhdl.std import *
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from migen.fhdl.specials import Memory
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from migen.bank.description import *
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from migen.genlib.record import *
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from miscope.std import *
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class Term(Module, AutoCSR):
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def __init__(self, width):
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self.width = width
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self.sink = Record(dat_layout(width))
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self.source = Record(hit_layout())
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self._trig = CSRStorage(width)
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self._mask = CSRStorage(width)
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###
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trig = self._trig.storage
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mask = self._mask.storage
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dat = self.sink.dat
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hit = self.source.hit
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self.comb += [
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hit.eq((dat & mask) == trig),
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self.source.stb.eq(self.sink.stb)
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]
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class RangeDetector(Module, AutoCSR):
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def __init__(self, width):
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self.width = width
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self.sink = Record(dat_layout(width))
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self.source = Record(hit_layout())
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self._low = CSRStorage(width)
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self._high = CSRStorage(width)
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###
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low = self._low.storage
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high = self._high.storage
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dat = self.sink.dat
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hit = self.source.hit
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self.comb += [
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hit.eq((dat >= low) & (dat <= high)),
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self.source.stb.eq(self.sink.stb)
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]
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class EdgeDetector(Module, AutoCSR):
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def __init__(self, width):
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self.width = width
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self.sink = Record(dat_layout(width))
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self.source = Record(hit_layout())
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self._rising_mask = CSRStorage(width)
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self._falling_mask = CSRStorage(width)
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self._both_mask = CSRStorage(width)
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###
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rising_mask = self._rising_mask.storage
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falling_mask = self._falling_mask.storage
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both_mask = self._both_mask.storage
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dat = self.sink.dat
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dat_d = Signal(width)
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rising_hit = Signal()
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falling_hit = Signal()
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both_hit = Signal()
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hit = self.source.hit
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self.sync += dat_d.eq(dat)
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self.comb += [
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rising_hit.eq(rising_mask & dat & ~dat_d),
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falling_hit.eq(rising_mask & ~dat & dat_d),
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both_hit.eq((both_mask & dat) != (both_mask & dat_d)),
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hit.eq(rising_hit | falling_hit | both_hit),
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self.source.stb.eq(self.sink.stb)
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]
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class Sum(Module, AutoCSR):
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def __init__(self, ports=4):
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self.sinks = [Record(hit_layout()) for p in range(ports)]
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self.source = Record(hit_layout())
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self._prog_we = CSRStorage()
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self._prog_adr = CSRStorage(ports) #FIXME
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self._prog_dat = CSRStorage()
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mem = Memory(1, 2**ports)
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lut_port = mem.get_port()
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prog_port = mem.get_port(write_capable=True)
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self.specials += mem, lut_port, prog_port
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###
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# Lut prog
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self.comb += [
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prog_port.we.eq(self._prog_we.storage),
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prog_port.adr.eq(self._prog_adr.storage),
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prog_port.dat_w.eq(self._prog_dat.storage)
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]
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# Lut read
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for i, sink in enumerate(self.sinks):
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self.comb += lut_port.adr[i].eq(sink.hit)
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# Drive source
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self.comb += [
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self.source.stb.eq(optree("&", [sink.stb for sink in self.sinks])),
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self.source.hit.eq(lut_port.dat_r),
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]
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class Trigger(Module, AutoCSR):
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def __init__(self, width, ports):
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self.width = width
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self.ports = ports
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self.submodules.sum = Sum(len(ports))
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for i, port in enumerate(ports):
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setattr(self.submodules, "port"+str(i), port)
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self.sink = Record(dat_layout(width))
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self.source = self.sum.source
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###
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for i, port in enumerate(ports):
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self.comb += [
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self.sink.connect(port.sink),
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port.source.connect(self.sum.sinks[i])
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]
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