87 lines
3.2 KiB
Python
87 lines
3.2 KiB
Python
from migen.fhdl.std import *
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from migen.bus import wishbone, csr
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from misoclib.mem.sdram.bus import dfi, lasmibus, wishbone2lasmi
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from misoclib.mem.sdram import minicon, lasmicon
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from misoclib.mem.sdram import dfii
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from misoclib.mem.sdram import memtest
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from misoclib.soc import Soc, mem_decoder
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class SDRAMSoC(SoC):
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csr_map = {
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"dfii": 6,
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"lasmicon": 7,
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"wishbone2lasmi": 8,
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"memtest_w": 9,
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"memtest_r": 10
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}
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csr_map.update(SoC.csr_map)
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def __init__(self, platform, clk_freq,
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ramcon_type="lasmicon",
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with_l2=True, l2_size=8192,
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with_memtest=False,
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**kwargs):
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SoC.__init__(self, platform, clk_freq, **kwargs)
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self.ramcon_type = ramcon_type
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self.with_l2 = with_l2
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self.l2_size = l2_size
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self.with_memtest = with_memtest
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self._sdram_phy_registered = False
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def register_sdram_phy(self, phy_dfi, phy_settings, sdram_geom, sdram_timing):
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if self._sdram_phy_registered:
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raise FinalizeError
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self._sdram_phy_registered = True
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# DFI
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self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a,
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phy_settings.dfi_d, phy_settings.nphases)
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self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, phy_dfi)
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# LASMICON
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if self.ramcon_type == "lasmicon":
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self.submodules.lasmicon = lasmicon.LASMIcon(phy_settings, sdram_geom, sdram_timing)
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self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave)
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self.submodules.lasmixbar = lasmibus.Crossbar([self.lasmicon.lasmic], self.lasmicon.nrowbits)
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if self.with_memtest:
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self.submodules.memtest_w = memtest.MemtestWriter(self.lasmixbar.get_master())
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self.submodules.memtest_r = memtest.MemtestReader(self.lasmixbar.get_master())
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if self.with_l2:
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self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master())
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sdram_size = 2**self.lasmicon.lasmic.aw*self.lasmicon.lasmic.dw*self.lasmicon.lasmic.nbanks//8
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self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, sdram_size)
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# MINICON
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elif self.ramcon_type == "minicon":
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if self.with_l2:
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raise ValueError("MINICON does not implement L2 cache (Use LASMICON or disable L2 cache (with_l2=False))")
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self.submodules.minicon = sdramcon = minicon.Minicon(phy_settings, sdram_geom, sdram_timing)
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self.submodules.dficon1 = dfi.Interconnect(sdramcon.dfi, self.dfii.slave)
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sdram_width = flen(sdramcon.bus.dat_r)
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sdram_size = 2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8
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if sdram_width == 32:
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self.register_mem("sdram", self.mem_map["sdram"], sdramcon.bus, sdram_size)
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elif sdram_width < 32:
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self.submodules.dc = wishbone.DownConverter(32, sdram_width)
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self.submodules.intercon = wishbone.InterconnectPointToPoint(self.dc.wishbone_o, sdramcon.bus)
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self.register_mem("sdram", self.mem_map["sdram"], self.dc.wishbone_i, sdram_size)
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else:
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raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
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else:
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raise ValueError("Unsupported SDRAM controller type: {}".format(self.ramcon_type))
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def do_finalize(self):
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if not self._sdram_phy_registered:
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raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
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SoC.do_finalize(self)
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