Sebastien Bourdeauducq 13af0ce556 fhdl: visit module (untested)		2012-11-09 16:00:11 +01:00
..
actorlib	actorlib/spi: typo	2012-10-15 21:21:42 +02:00
bank	bank/description: regprefix	2012-10-15 21:21:59 +02:00
bus	bus/csr: configurable data width	2012-08-26 21:19:34 +02:00
corelogic	corelogic/ReorderBuffer: do not touch empty count when issuing and reading at the same time	2012-07-13 20:21:04 +02:00
fhdl	fhdl: visit module (untested)	2012-11-09 16:00:11 +01:00
flow	flow/isd: add freeze register	2012-08-04 23:39:52 +02:00
pytholite	pytholith: add register muxes	2012-11-08 21:49:20 +01:00
sim	Multi-clock design support + new instance API	2012-09-10 23:45:02 +02:00
transform	transform/unroll_sync: autodetect in/out	2012-10-15 20:32:07 +02:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00