276 lines
6.6 KiB
Python
276 lines
6.6 KiB
Python
import math
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from migen.fhdl.std import *
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from migen.fhdl.decorators import ModuleTransformer
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from migen.genlib.resetsync import *
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from migen.genlib.fsm import *
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from migen.genlib.record import *
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from migen.genlib.misc import chooser, optree, Counter, Timeout
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from migen.genlib.cdc import *
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from migen.flow.actor import *
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from migen.flow.plumbing import Multiplexer, Demultiplexer
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from migen.actorlib.fifo import *
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from migen.actorlib.structuring import Pipeline, Converter
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from migen.actorlib.packet import Buffer
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from migen.actorlib.misc import BufferizeEndpoints
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from migen.actorlib.packet import HeaderField, Header
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bitrates = {
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"sata_gen3": 6.0,
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"sata_gen2": 3.0,
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"sata_gen1": 1.5,
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}
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frequencies = {
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"sata_gen3": 150.0,
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"sata_gen2": 75.0,
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"sata_gen1": 37.5,
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}
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# PHY / Link Layers
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primitives = {
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"ALIGN": 0x7B4A4ABC,
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"CONT": 0X9999AA7C,
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"SYNC": 0xB5B5957C,
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"R_RDY": 0x4A4A957C,
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"R_OK": 0x3535B57C,
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"R_ERR": 0x5656B57C,
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"R_IP": 0X5555B57C,
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"X_RDY": 0x5757B57C,
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"CONT": 0x9999AA7C,
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"WTRM": 0x5858B57C,
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"SOF": 0x3737B57C,
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"EOF": 0xD5D5B57C,
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"HOLD": 0xD5D5AA7C,
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"HOLDA": 0X9595AA7C
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}
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def is_primitive(dword):
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for k, v in primitives.items():
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if dword == v:
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return True
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return False
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def decode_primitive(dword):
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for k, v in primitives.items():
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if dword == v:
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return k
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return ""
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def phy_description(dw):
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layout = [
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("data", dw),
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("charisk", dw//8),
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]
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return EndpointDescription(layout, packetized=False)
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def link_description(dw):
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layout = [
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("d", dw),
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("error", 1)
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]
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return EndpointDescription(layout, packetized=True)
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# Transport Layer
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fis_max_dwords = 2048
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fis_types = {
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"REG_H2D": 0x27,
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"REG_D2H": 0x34,
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"DMA_ACTIVATE_D2H": 0x39,
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"PIO_SETUP_D2H": 0x5F,
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"DATA": 0x46
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}
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fis_reg_h2d_header_length = 5
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fis_reg_h2d_header_fields = {
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"type": HeaderField(0*4, 0, 8),
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"pm_port": HeaderField(0*4, 8, 4),
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"c": HeaderField(0*4, 15, 1),
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"command": HeaderField(0*4, 16, 8),
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"features_lsb": HeaderField(0*4, 24, 8),
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"lba_lsb": HeaderField(1*4, 0, 24),
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"device": HeaderField(1*4, 24, 8),
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"lba_msb": HeaderField(2*4, 0, 24),
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"features_msb": HeaderField(2*4, 24, 8),
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"count": HeaderField(3*4, 0, 16),
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"icc": HeaderField(3*4, 16, 8),
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"control": HeaderField(3*4, 24, 8)
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}
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fis_reg_h2d_header = Header(fis_reg_h2d_header_fields,
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fis_reg_h2d_header_length,
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swap_field_bytes=False)
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fis_reg_d2h_header_length = 5
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fis_reg_d2h_header_fields = {
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"type": HeaderField(0*4, 0, 8),
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"pm_port": HeaderField(0*4, 8, 4),
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"i": HeaderField(0*4, 14, 1),
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"status": HeaderField(0*4, 16, 8),
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"error": HeaderField(0*4, 24, 8),
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"lba_lsb": HeaderField(1*4, 0, 24),
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"device": HeaderField(1*4, 24, 8),
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"lba_msb": HeaderField(2*4, 0, 24),
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"count": HeaderField(3*4, 0, 16)
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}
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fis_reg_d2h_header = Header(fis_reg_d2h_header_fields,
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fis_reg_d2h_header_length,
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swap_field_bytes=False)
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fis_dma_activate_d2h_header_length = 1
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fis_dma_activate_d2h_header_fields = {
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"type": HeaderField(0*4, 0, 8),
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"pm_port": HeaderField(0*4, 8, 4)
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}
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fis_dma_activate_d2h_header = Header(fis_dma_activate_d2h_header_fields,
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fis_dma_activate_d2h_header_length,
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swap_field_bytes=False)
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fis_pio_setup_d2h_header_length = 5
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fis_pio_setup_d2h_header_fields = {
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"type": HeaderField(0*4, 0, 8),
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"pm_port": HeaderField(0*4, 8, 4),
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"d": HeaderField(0*4, 13, 1),
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"i": HeaderField(0*4, 14, 1),
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"status": HeaderField(0*4, 16, 8),
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"error": HeaderField(0*4, 24, 8),
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"lba_lsb": HeaderField(1*4, 0, 24),
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"lba_msb": HeaderField(2*4, 0, 24),
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"count": HeaderField(3*4, 0, 16),
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"transfer_count": HeaderField(4*4, 0, 16),
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}
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fis_pio_setup_d2h_header = Header(fis_pio_setup_d2h_header_fields,
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fis_pio_setup_d2h_header_length,
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swap_field_bytes=False)
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fis_data_header_length = 1
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fis_data_header_fields = {
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"type": HeaderField(0, 0, 8)
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}
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fis_data_header = Header(fis_data_header_fields,
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fis_data_header_length,
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swap_field_bytes=False)
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def transport_tx_description(dw):
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layout = [
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("type", 8),
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("pm_port", 4),
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("c", 1),
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("command", 8),
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("features", 16),
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("lba", 48),
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("device", 8),
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("count", 16),
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("icc", 8),
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("control", 8),
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("data", dw)
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]
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return EndpointDescription(layout, packetized=True)
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def transport_rx_description(dw):
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layout = [
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("type", 8),
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("pm_port", 4),
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("r", 1),
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("d", 1),
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("i", 1),
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("status", 8),
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("errors", 8),
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("lba", 48),
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("device", 8),
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("count", 16),
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("transfer_count", 16),
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("data", dw),
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("error", 1)
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]
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return EndpointDescription(layout, packetized=True)
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# Command Layer
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regs = {
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"WRITE_DMA_EXT": 0x35,
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"READ_DMA_EXT": 0x25,
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"IDENTIFY_DEVICE": 0xEC
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}
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reg_d2h_status = {
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"bsy": 7,
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"drdy": 6,
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"df": 5,
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"se": 5,
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"dwe": 4,
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"drq": 3,
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"ae": 2,
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"sns": 1,
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"cc": 0,
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"err": 0
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}
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def command_tx_description(dw):
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layout = [
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("write", 1),
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("read", 1),
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("identify", 1),
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("sector", 48),
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("count", 16),
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("data", dw)
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]
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return EndpointDescription(layout, packetized=True)
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def command_rx_description(dw):
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layout = [
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("write", 1),
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("read", 1),
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("identify", 1),
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("last", 1),
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("failed", 1),
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("data", dw)
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]
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return EndpointDescription(layout, packetized=True)
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def command_rx_cmd_description(dw):
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layout = [
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("write", 1),
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("read", 1),
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("identify", 1),
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("last", 1),
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("failed", 1)
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]
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return EndpointDescription(layout, packetized=False)
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def command_rx_data_description(dw):
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layout = [
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("data", dw)
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]
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return EndpointDescription(layout, packetized=True)
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# HDD
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logical_sector_size = 512 # constant since all HDDs use this
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def dwords2sectors(n):
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return math.ceil(n*4/logical_sector_size)
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def sectors2dwords(n):
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return n*logical_sector_size//4
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